/*
 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED 
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF 
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. 
 * MICRONAS SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, 
 * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 * (c) 2022 TDK-Micronas
 *
 * @file     HVC5221D_B1.h
 * @brief    CMSIS HeaderFile
 * @version  1.0
 * @date     31. May 2022
 * @note     Generated by SVDConv V3.3.39 on Tuesday, 31.05.2022 12:40:57
 *           from File 'HVC5221D_B1.svd',
 *           last modified on Tuesday, 31.05.2022 10:39:31
 */



/** @addtogroup TDK-Micronas
  * @{
  */


/** @addtogroup HVC5221D_B1
  * @{
  */


#ifndef HVC5221D_B1_H
#define HVC5221D_B1_H

#ifdef __cplusplus
extern "C" {
#endif


/** @addtogroup Configuration_of_CMSIS
  * @{
  */



/* =========================================================================================================================== */
/* ================                                Interrupt Number Definition                                ================ */
/* =========================================================================================================================== */

typedef enum {
/* =======================================  ARM Cortex-M3 Specific Interrupt Numbers  ======================================== */
  Reset_IRQn                = -15,              /*!< -15  Reset Vector, invoked on Power up and warm reset                     */
  NonMaskableInt_IRQn       = -14,              /*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */
  HardFault_IRQn            = -13,              /*!< -13  Hard Fault, all classes of Fault                                     */
  MemoryManagement_IRQn     = -12,              /*!< -12  Memory Management, MPU mismatch, including Access Violation
                                                     and No Match                                                              */
  BusFault_IRQn             = -11,              /*!< -11  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
                                                     related Fault                                                             */
  UsageFault_IRQn           = -10,              /*!< -10  Usage Fault, i.e. Undef Instruction, Illegal State Transition        */
  SVCall_IRQn               =  -5,              /*!< -5 System Service Call via SVC instruction                                */
  DebugMonitor_IRQn         =  -4,              /*!< -4 Debug Monitor                                                          */
  PendSV_IRQn               =  -2,              /*!< -2 Pendable request for system service                                    */
  SysTick_IRQn              =  -1,              /*!< -1 System Tick Timer                                                      */
/* ========================================  HVC5221D_B1 Specific Interrupt Numbers  ========================================= */
  LGPIO_IRQn                =   0,              /*!< 0  LGPIO Port Interrupt                                                   */
  TIM0_IRQn                 =   1,              /*!< 1  Timer 0 Interrupt                                                      */
  TIM1_IRQn                 =   2,              /*!< 2  Timer 1 Interrupt                                                      */
  LINUART_IRQn              =   3,              /*!< 3  LINUART Interrupt                                                      */
  EPWM0_IRQn                =   4,              /*!< 4  EPWM0 Interrupt                                                        */
  EPWM1_IRQn                =   5,              /*!< 5  EPWM1 Interrupt                                                        */
  EPWM2_IRQn                =   6,              /*!< 6  EPWM2 Interrupt                                                        */
  EPWMOC_IRQn               =   7,              /*!< 7  EPWM MOUT Overcurrent Interrupt                                        */
  CAPCOM0_IRQn              =   8,              /*!< 8  CAPCOM0 Interrupt                                                      */
  CAPCOM1_IRQn              =   9,              /*!< 9  CAPCOM1 Interrupt                                                      */
  CAPCOM2_IRQn              =  10,              /*!< 10 CAPCOM2 Interrupt                                                      */
  ADC_IRQn                  =  11,              /*!< 11 ADC Interrupt                                                          */
  BEMFC_IRQn                =  12,              /*!< 12 BEMFC Interrupt                                                        */
  SPI_IRQn                  =  13,              /*!< 13 SPI Interrupt                                                          */
  LIN_IRQn                  =  14,              /*!< 14 LIN Port Interrupt                                                     */
  FLASH_IRQn                =  15,              /*!< 15 Flash ECC Interrupt                                                    */
  BVDDUV_IRQn               =  16,              /*!< 16 BVDD Undervoltage Warning Interrupt                                    */
  BVDDOV_IRQn               =  17,              /*!< 17 BVDD Overvoltage Warning Interrupt                                     */
  CPOFF_IRQn                =  18               /*!< 18 Chargpump Off Warning Interrupt                                        */
} IRQn_Type;



/* =========================================================================================================================== */
/* ================                           Processor and Core Peripheral Section                           ================ */
/* =========================================================================================================================== */

/* ===========================  Configuration of the ARM Cortex-M3 Processor and Core Peripherals  =========================== */
#define __CM3_REV                 0x0201U       /*!< CM3 Core Revision                                                         */
#define __NVIC_PRIO_BITS               3        /*!< Number of Bits used for Priority Levels                                   */
#define __Vendor_SysTickConfig         0        /*!< Set to 1 if different SysTick Config is used                              */
#define __MPU_PRESENT                  1        /*!< MPU present                                                               */
#define __FPU_PRESENT                  0        /*!< FPU present                                                               */


/** @} */ /* End of group Configuration_of_CMSIS */

#include "core_cm3.h"                           /*!< ARM Cortex-M3 processor and core peripherals                              */
#include "system_HVC5221D_B1.h"                 /*!< HVC5221D_B1 System                                                        */

#ifndef __IM                                    /*!< Fallback for older CMSIS versions                                         */
  #define __IM   __I
#endif
#ifndef __OM                                    /*!< Fallback for older CMSIS versions                                         */
  #define __OM   __O
#endif
#ifndef __IOM                                   /*!< Fallback for older CMSIS versions                                         */
  #define __IOM  __IO
#endif


/* ========================================  Start of section using anonymous unions  ======================================== */
#if defined (__CC_ARM)
  #pragma push
  #pragma anon_unions
#elif defined (__ICCARM__)
  #pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic push
  #pragma clang diagnostic ignored "-Wc11-extensions"
  #pragma clang diagnostic ignored "-Wreserved-id-macro"
  #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
  #pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning 586
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#else
  #warning Not supported compiler type
#endif


/* =========================================================================================================================== */
/* ================                              Device Specific Cluster Section                              ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_clusters
  * @{
  */


/**
  * @brief FLASH_MAIN [MAIN] (MAIN Array)
  */
typedef struct {
  __IOM uint32_t  WORD[64];                     /*!< (@ 0x00000000) MAIN Data Sector                                           */
} FLASH_MAIN_Type;                              /*!< Size = 256 (0x100)                                                        */


/** @} */ /* End of group Device_Peripheral_clusters */


/* =========================================================================================================================== */
/* ================                            Device Specific Peripheral Section                             ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_peripherals
  * @{
  */



/* =========================================================================================================================== */
/* ================                                          SYSCTRL                                          ================ */
/* =========================================================================================================================== */


/**
  * @brief System Control (SYSCTRL)
  */

typedef struct {                                /*!< (@ 0x40000000) SYSCTRL Structure                                          */
  
  union {
    __IOM uint32_t CCR;                         /*!< (@ 0x00000000) CGU Clock Control Register                                 */
    
    struct {
      __IOM uint32_t CPUCM      : 1;            /*!< [0..0] CPU Clock Mode                                                     */
            uint32_t            : 7;
      __IOM uint32_t CP_DIS     : 1;            /*!< [8..8] Charge Pump Disable                                                */
            uint32_t            : 23;
    } CCR_b;
  } ;
  
  union {
    __IOM uint32_t CPUDIV;                      /*!< (@ 0x00000004) CPU Clock Divider Register                                 */
    
    struct {
      __IOM uint32_t CPUDIV     : 3;            /*!< [2..0] CPU Clock Divider Setting                                          */
            uint32_t            : 29;
    } CPUDIV_b;
  } ;
  
  union {
    __IOM uint32_t DBGSTOP;                     /*!< (@ 0x00000008) Debug Stop Register                                        */
    
    struct {
      __IOM uint32_t DWDGS      : 1;            /*!< [0..0] DWDG Debug Stop                                                    */
      __IOM uint32_t WWDGS      : 1;            /*!< [1..1] WWDG Debug Stop                                                    */
      __IOM uint32_t TIMERS     : 1;            /*!< [2..2] Timer0 and Timer1 Debug Stop                                       */
      __IOM uint32_t EPWMS      : 1;            /*!< [3..3] EPWM Debug Stop                                                    */
      __IOM uint32_t CAPCOMS    : 1;            /*!< [4..4] CAPCOM Debug Stop                                                  */
      __IOM uint32_t ADCS       : 1;            /*!< [5..5] ADC Debug Stop                                                     */
      __IOM uint32_t LINUARTS   : 1;            /*!< [6..6] LINUART Debug Stop                                                 */
      __IOM uint32_t SPIS       : 1;            /*!< [7..7] SPI Debug Stop                                                     */
            uint32_t            : 24;
    } DBGSTOP_b;
  } ;
  __IM  uint32_t  RESERVED;
  
  union {
    __IOM uint32_t ERMCR;                       /*!< (@ 0x00000010) ERM Control Register                                       */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] ERM Enable                                                         */
            uint32_t            : 31;
    } ERMCR_b;
  } ;
  __IM  uint32_t  RESERVED1[3];
  
  union {
    __IOM uint32_t RWCR;                        /*!< (@ 0x00000020) Reset and Wakeup Control Register                          */
    
    struct {
      __IOM uint32_t FHR        : 1;            /*!< [0..0] Forced Hardware Reset                                              */
            uint32_t            : 15;
      __IOM uint32_t MWK        : 1;            /*!< [16..16] MOUT3 Wakeup Enable                                              */
            uint32_t            : 15;
    } RWCR_b;
  } ;
  
  union {
    __IOM uint32_t RWSR;                        /*!< (@ 0x00000024) Reset and Wakeup Status Register                           */
    
    struct {
      __IOM uint32_t FHR        : 1;            /*!< [0..0] Forced Hardware Reset                                              */
      __IOM uint32_t POR        : 1;            /*!< [1..1] Power On Reset                                                     */
      __IOM uint32_t OTD        : 1;            /*!< [2..2] OTD Reset                                                          */
      __IOM uint32_t RET        : 1;            /*!< [3..3] Retention Mode Reset                                               */
      __IOM uint32_t DWDGR      : 1;            /*!< [4..4] Digital Watchdog Reset                                             */
      __IOM uint32_t WWDGR      : 1;            /*!< [5..5] Window Watchdog Reset                                              */
      __IOM uint32_t SDA        : 1;            /*!< [6..6] SDA Reset                                                          */
            uint32_t            : 9;
      __IOM uint32_t MWK        : 1;            /*!< [16..16] MOUT3 Wakeup                                                     */
      __IOM uint32_t LWK        : 1;            /*!< [17..17] LIN Wakeup                                                       */
            uint32_t            : 14;
    } RWSR_b;
  } ;
  __IM  uint32_t  RESERVED2[2];
  
  union {
    __IOM uint32_t PCR;                         /*!< (@ 0x00000030) Power Control Register                                     */
    
    struct {
      __IOM uint32_t GTS        : 1;            /*!< [0..0] Go To SLEEP Mode                                                   */
            uint32_t            : 31;
    } PCR_b;
  } ;
  __IOM uint32_t  PCRULA;                       /*!< (@ 0x00000034) Power Control Unlock Register A                            */
  __IM  uint32_t  RESERVED3;
  __IOM uint32_t  PCRULB;                       /*!< (@ 0x0000003C) Power Control Unlock Register B                            */
  
  union {
    __IOM uint32_t SR;                          /*!< (@ 0x00000040) Status Register                                            */
    
    struct {
      __IM  uint32_t BVDDUV     : 1;            /*!< [0..0] BVDD Undervoltage Level                                            */
      __IM  uint32_t BVDDOV     : 1;            /*!< [1..1] BVDD Overvoltage Level                                             */
            uint32_t            : 6;
      __IM  uint32_t CPRDY      : 1;            /*!< [8..8] Chargepump Ready                                                   */
            uint32_t            : 23;
    } SR_b;
  } ;
  
  union {
    __IOM uint32_t IEN;                         /*!< (@ 0x00000044) SYSCTRL Interrupt Enable Register                          */
    
    struct {
      __IOM uint32_t BVDDUV     : 1;            /*!< [0..0] BVDD Undervoltage Interrupt Enable                                 */
      __IOM uint32_t BVDDOV     : 1;            /*!< [1..1] BVDD Overvoltage Interrupt Enable                                  */
            uint32_t            : 6;
      __IOM uint32_t CPOFF      : 1;            /*!< [8..8] Chargepump Off Interrupt Enable                                    */
            uint32_t            : 23;
    } IEN_b;
  } ;
  
  union {
    __IOM uint32_t IPND;                        /*!< (@ 0x00000048) SYSCTRL Interrupt Pending Register                         */
    
    struct {
      __IOM uint32_t BVDDUV     : 1;            /*!< [0..0] BVDD Undervoltage Interrupt Pending                                */
      __IOM uint32_t BVDDOV     : 1;            /*!< [1..1] BVDD Overvoltage Interrupt Pending                                 */
            uint32_t            : 6;
      __IOM uint32_t CPOFF      : 1;            /*!< [8..8] Chargepump Off Interrupt Pending                                   */
            uint32_t            : 23;
    } IPND_b;
  } ;
  
  union {
    __IOM uint32_t EIPND;                       /*!< (@ 0x0000004C) SYSCTRL Enabled Interrupt Pending Register                 */
    
    struct {
      __IOM uint32_t BVDDUV     : 1;            /*!< [0..0] Enabled BVDD Undervoltage Interrupt Pending                        */
      __IOM uint32_t BVDDOV     : 1;            /*!< [1..1] Enabled BVDD Overvoltage Interrupt Pending                         */
            uint32_t            : 6;
      __IOM uint32_t CPOFF      : 1;            /*!< [8..8] Enabled Chargepump Off Interrupt Pending                           */
            uint32_t            : 23;
    } EIPND_b;
  } ;
} SYSCTRL_Type;                                 /*!< Size = 80 (0x50)                                                          */



/* =========================================================================================================================== */
/* ================                                           LGPIO                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief General purpose low-voltage IOs (LGPIO)
  */

typedef struct {                                /*!< (@ 0x40001000) LGPIO Structure                                            */
  
  union {
    __IOM uint32_t DO;                          /*!< (@ 0x00000000) LGPIO Data Out Register                                    */
    
    struct {
      __IOM uint32_t DO0        : 1;            /*!< [0..0] LGPIO0 Data Out                                                    */
      __IOM uint32_t DO1        : 1;            /*!< [1..1] LGPIO1 Data Out                                                    */
      __IOM uint32_t DO2        : 1;            /*!< [2..2] LGPIO2 Data Out                                                    */
      __IOM uint32_t DO3        : 1;            /*!< [3..3] LGPIO3 Data Out                                                    */
      __IOM uint32_t DO4        : 1;            /*!< [4..4] LGPIO4 Data Out                                                    */
      __IOM uint32_t DO5        : 1;            /*!< [5..5] LGPIO5 Data Out                                                    */
      __IOM uint32_t DO6        : 1;            /*!< [6..6] LGPIO6 Data Out                                                    */
            uint32_t            : 25;
    } DO_b;
  } ;
  
  union {
    __IM  uint32_t DI;                          /*!< (@ 0x00000004) LGPIO Data In Register                                     */
    
    struct {
      __IM  uint32_t DI0        : 1;            /*!< [0..0] LGPIO0 Data In                                                     */
      __IM  uint32_t DI1        : 1;            /*!< [1..1] LGPIO1 Data In                                                     */
      __IM  uint32_t DI2        : 1;            /*!< [2..2] LGPIO2 Data In                                                     */
      __IM  uint32_t DI3        : 1;            /*!< [3..3] LGPIO3 Data In                                                     */
      __IM  uint32_t DI4        : 1;            /*!< [4..4] LGPIO4 Data In                                                     */
      __IM  uint32_t DI5        : 1;            /*!< [5..5] LGPIO5 Data In                                                     */
      __IM  uint32_t DI6        : 1;            /*!< [6..6] LGPIO6 Data In                                                     */
            uint32_t            : 25;
    } DI_b;
  } ;
  
  union {
    __IOM uint32_t DD;                          /*!< (@ 0x00000008) LGPIO Data Direction Register                              */
    
    struct {
      __IOM uint32_t DD0        : 1;            /*!< [0..0] LGPIO0 Data Direction                                              */
      __IOM uint32_t DD1        : 1;            /*!< [1..1] LGPIO1 Data Direction                                              */
      __IOM uint32_t DD2        : 1;            /*!< [2..2] LGPIO2 Data Direction                                              */
      __IOM uint32_t DD3        : 1;            /*!< [3..3] LGPIO3 Data Direction                                              */
      __IOM uint32_t DD4        : 1;            /*!< [4..4] LGPIO4 Data Direction                                              */
      __IOM uint32_t DD5        : 1;            /*!< [5..5] LGPIO5 Data Direction                                              */
      __IOM uint32_t DD6        : 1;            /*!< [6..6] LGPIO6 Data Direction                                              */
            uint32_t            : 25;
    } DD_b;
  } ;
  
  union {
    __IOM uint32_t C0;                          /*!< (@ 0x0000000C) LGPIO Config Register 0                                    */
    
    struct {
      __IOM uint32_t C00        : 1;            /*!< [0..0] LGPIO0 Config 0                                                    */
      __IOM uint32_t C01        : 1;            /*!< [1..1] LGPIO1 Config 0                                                    */
      __IOM uint32_t C02        : 1;            /*!< [2..2] LGPIO2 Config 0                                                    */
      __IOM uint32_t C03        : 1;            /*!< [3..3] LGPIO3 Config 0                                                    */
      __IOM uint32_t C04        : 1;            /*!< [4..4] LGPIO4 Config 0                                                    */
      __IOM uint32_t C05        : 1;            /*!< [5..5] LGPIO5 Config 0                                                    */
      __IOM uint32_t C06        : 1;            /*!< [6..6] LGPIO6 Config 0                                                    */
            uint32_t            : 25;
    } C0_b;
  } ;
  
  union {
    __IOM uint32_t C1;                          /*!< (@ 0x00000010) LGPIO Config Register 1                                    */
    
    struct {
      __IOM uint32_t C10        : 1;            /*!< [0..0] LGPIO0 Config 1                                                    */
      __IOM uint32_t C11        : 1;            /*!< [1..1] LGPIO1 Config 1                                                    */
      __IOM uint32_t C12        : 1;            /*!< [2..2] LGPIO2 Config 1                                                    */
      __IOM uint32_t C13        : 1;            /*!< [3..3] LGPIO3 Config 1                                                    */
      __IOM uint32_t C14        : 1;            /*!< [4..4] LGPIO4 Config 1                                                    */
      __IOM uint32_t C15        : 1;            /*!< [5..5] LGPIO5 Config 1                                                    */
      __IOM uint32_t C16        : 1;            /*!< [6..6] LGPIO6 Config 1                                                    */
            uint32_t            : 25;
    } C1_b;
  } ;
  
  union {
    __IOM uint32_t AOS;                         /*!< (@ 0x00000014) LGPIO Alternative Output Select                            */
    
    struct {
      __IOM uint32_t AOS0       : 1;            /*!< [0..0] LGPIO0 Alternative Output Selection                                */
            uint32_t            : 1;
      __IOM uint32_t AOS1       : 1;            /*!< [2..2] LGPIO1 Alternative Output Selection                                */
            uint32_t            : 1;
      __IOM uint32_t AOS2       : 1;            /*!< [4..4] LGPIO2 Alternative Output Selection                                */
            uint32_t            : 1;
      __IOM uint32_t AOS3       : 1;            /*!< [6..6] LGPIO3 Alternative Output Selection                                */
            uint32_t            : 1;
      __IOM uint32_t AOS4       : 1;            /*!< [8..8] LGPIO4 Alternative Output Selection                                */
            uint32_t            : 1;
      __IOM uint32_t AOS5       : 1;            /*!< [10..10] LGPIO5 Alternative Output Selection                              */
            uint32_t            : 1;
      __IOM uint32_t AOS6       : 1;            /*!< [12..12] LGPIO6 Alternative Output Selection                              */
            uint32_t            : 19;
    } AOS_b;
  } ;
  
  union {
    __IOM uint32_t AIS;                         /*!< (@ 0x00000018) GPIO Alternative Input Select                              */
    
    struct {
      __IOM uint32_t AIS0       : 1;            /*!< [0..0] TIMER0_IN Input Selection                                          */
            uint32_t            : 1;
      __IOM uint32_t AIS1       : 1;            /*!< [2..2] TIMER1_IN Input Selection                                          */
            uint32_t            : 1;
      __IOM uint32_t AIS2       : 1;            /*!< [4..4] LINUART_RX Input Selection                                         */
            uint32_t            : 1;
      __IOM uint32_t AIS3       : 1;            /*!< [6..6] CAPCOM0_IN Input Selection                                         */
            uint32_t            : 1;
      __IOM uint32_t AIS4       : 1;            /*!< [8..8] CAPCOM1_IN Input Selection                                         */
            uint32_t            : 1;
      __IOM uint32_t AIS5       : 1;            /*!< [10..10] CAPCOM2_IN Input Selection                                       */
            uint32_t            : 1;
      __IOM uint32_t AIS6       : 1;            /*!< [12..12] SPI_MISO Input Selection                                         */
            uint32_t            : 19;
    } AIS_b;
  } ;
  
  union {
    __IOM uint32_t IRISE;                       /*!< (@ 0x0000001C) LGPIO Rising Edge Interrupt Enable Register                */
    
    struct {
      __IOM uint32_t IRISE0     : 1;            /*!< [0..0] LGPIO0 Rising Edge Interrupt Enable                                */
      __IOM uint32_t IRISE1     : 1;            /*!< [1..1] LGPIO1 Rising Edge Interrupt Enable                                */
      __IOM uint32_t IRISE2     : 1;            /*!< [2..2] LGPIO2 Rising Edge Interrupt Enable                                */
      __IOM uint32_t IRISE3     : 1;            /*!< [3..3] LGPIO3 Rising Edge Interrupt Enable                                */
      __IOM uint32_t IRISE4     : 1;            /*!< [4..4] LGPIO4 Rising Edge Interrupt Enable                                */
      __IOM uint32_t IRISE5     : 1;            /*!< [5..5] LGPIO5 Rising Edge Interrupt Enable                                */
      __IOM uint32_t IRISE6     : 1;            /*!< [6..6] LGPIO6 Rising Edge Interrupt Enable                                */
            uint32_t            : 25;
    } IRISE_b;
  } ;
  
  union {
    __IOM uint32_t IFALL;                       /*!< (@ 0x00000020) LGPIO Falling Edge Interrupt Enable Register               */
    
    struct {
      __IOM uint32_t IFALL0     : 1;            /*!< [0..0] LGPIO0 Falling Edge Interrupt Enable                               */
      __IOM uint32_t IFALL1     : 1;            /*!< [1..1] LGPIO1 Falling Edge Interrupt Enable                               */
      __IOM uint32_t IFALL2     : 1;            /*!< [2..2] LGPIO2 Falling Edge Interrupt Enable                               */
      __IOM uint32_t IFALL3     : 1;            /*!< [3..3] LGPIO3 Falling Edge Interrupt Enable                               */
      __IOM uint32_t IFALL4     : 1;            /*!< [4..4] LGPIO4 Falling Edge Interrupt Enable                               */
      __IOM uint32_t IFALL5     : 1;            /*!< [5..5] LGPIO5 Falling Edge Interrupt Enable                               */
      __IOM uint32_t IFALL6     : 1;            /*!< [6..6] LGPIO6 Falling Edge Interrupt Enable                               */
            uint32_t            : 25;
    } IFALL_b;
  } ;
  
  union {
    __IOM uint32_t GIF;                         /*!< (@ 0x00000024) LGPIO Input Filter Register                                */
    
    struct {
      __IOM uint32_t GIF        : 3;            /*!< [2..0] LGPIO Input Filter                                                 */
            uint32_t            : 29;
    } GIF_b;
  } ;
  
  union {
    __IOM uint32_t IEN;                         /*!< (@ 0x00000028) LGPIO Interrupt Enable Register                            */
    
    struct {
      __IOM uint32_t GPIO0      : 1;            /*!< [0..0] LGPIO0 Interrupt Enable                                            */
      __IOM uint32_t GPIO1      : 1;            /*!< [1..1] LGPIO1 Interrupt Enable                                            */
      __IOM uint32_t GPIO2      : 1;            /*!< [2..2] LGPIO2 Interrupt Enable                                            */
      __IOM uint32_t GPIO3      : 1;            /*!< [3..3] LGPIO3 Interrupt Enable                                            */
      __IOM uint32_t GPIO4      : 1;            /*!< [4..4] LGPIO4 Interrupt Enable                                            */
      __IOM uint32_t GPIO5      : 1;            /*!< [5..5] LGPIO5 Interrupt Enable                                            */
      __IOM uint32_t GPIO6      : 1;            /*!< [6..6] LGPIO6 Interrupt Enable                                            */
            uint32_t            : 25;
    } IEN_b;
  } ;
  
  union {
    __IOM uint32_t IPND;                        /*!< (@ 0x0000002C) LGPIO Interrupt Pending Register                           */
    
    struct {
      __IOM uint32_t GPIO0      : 1;            /*!< [0..0] LGPIO0 Interrupt Pending                                           */
      __IOM uint32_t GPIO1      : 1;            /*!< [1..1] LGPIO1 Interrupt Pending                                           */
      __IOM uint32_t GPIO2      : 1;            /*!< [2..2] LGPIO2 Interrupt Pending                                           */
      __IOM uint32_t GPIO3      : 1;            /*!< [3..3] LGPIO3 Interrupt Pending                                           */
      __IOM uint32_t GPIO4      : 1;            /*!< [4..4] LGPIO4 Interrupt Pending                                           */
      __IOM uint32_t GPIO5      : 1;            /*!< [5..5] LGPIO5 Interrupt Pending                                           */
      __IOM uint32_t GPIO6      : 1;            /*!< [6..6] LGPIO6 Interrupt Pending                                           */
            uint32_t            : 25;
    } IPND_b;
  } ;
  
  union {
    __IOM uint32_t EIPND;                       /*!< (@ 0x00000030) LGPIO Enabled Interrupt Pending Register                   */
    
    struct {
      __IOM uint32_t GPIO0      : 1;            /*!< [0..0] LGPIO0 Enabled Interrupt Pending                                   */
      __IOM uint32_t GPIO1      : 1;            /*!< [1..1] LGPIO1 Enabled Interrupt Pending                                   */
      __IOM uint32_t GPIO2      : 1;            /*!< [2..2] LGPIO2 Enabled Interrupt Pending                                   */
      __IOM uint32_t GPIO3      : 1;            /*!< [3..3] LGPIO3 Enabled Interrupt Pending                                   */
      __IOM uint32_t GPIO4      : 1;            /*!< [4..4] LGPIO4 Enabled Interrupt Pending                                   */
      __IOM uint32_t GPIO5      : 1;            /*!< [5..5] LGPIO5 Enabled Interrupt Pending                                   */
      __IOM uint32_t GPIO6      : 1;            /*!< [6..6] LGPIO6 Enabled Interrupt Pending                                   */
            uint32_t            : 25;
    } EIPND_b;
  } ;
} LGPIO_Type;                                   /*!< Size = 52 (0x34)                                                          */



/* =========================================================================================================================== */
/* ================                                           TIM0                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief 16bit general purpose timer (TIM0)
  */

typedef struct {                                /*!< (@ 0x40002000) TIM0 Structure                                             */
  
  union {
    __IOM uint32_t CR;                          /*!< (@ 0x00000000) Timer Control Register                                     */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] Timer Enable                                                       */
      __IOM uint32_t CM         : 1;            /*!< [1..1] Clock Multiplexer                                                  */
      __IOM uint32_t MOD        : 2;            /*!< [3..2] Mode Selection                                                     */
      __IOM uint32_t CIF        : 3;            /*!< [6..4] Capture Input Filter                                               */
            uint32_t            : 1;
      __IOM uint32_t CIP        : 2;            /*!< [9..8] Capture Input Polarity                                             */
      __IOM uint32_t ARBE       : 1;            /*!< [10..10] Auto-Reload Register Buffer Enable                               */
      __IOM uint32_t CCBE       : 1;            /*!< [11..11] Capture/Compare Register Buffer Enable                           */
      __IOM uint32_t UEM        : 1;            /*!< [12..12] Update Event Mode                                                */
      __IOM uint32_t UIM        : 1;            /*!< [13..13] Update Interrupt Mode                                            */
      __IOM uint32_t TU         : 1;            /*!< [14..14] Trigger Timer Update                                             */
      __IOM uint32_t CCU        : 1;            /*!< [15..15] Trigger Capture/Compare Update                                   */
      __IOM uint32_t OCM        : 3;            /*!< [18..16] Output Control Mode                                              */
            uint32_t            : 13;
    } CR_b;
  } ;
  
  union {
    __IOM uint32_t CNT;                         /*!< (@ 0x00000004) Timer Counter Register                                     */
    
    struct {
      __IOM uint32_t CNT        : 16;           /*!< [15..0] Counter Value                                                     */
            uint32_t            : 16;
    } CNT_b;
  } ;
  
  union {
    __IOM uint32_t PS;                          /*!< (@ 0x00000008) Timer Prescaler Register                                   */
    
    struct {
      __IOM uint32_t PS         : 16;           /*!< [15..0] Prescaler Value                                                   */
            uint32_t            : 16;
    } PS_b;
  } ;
  
  union {
    __IOM uint32_t AR;                          /*!< (@ 0x0000000C) Timer Auto-Reload Register                                 */
    
    struct {
      __IOM uint32_t AR         : 16;           /*!< [15..0] Auto-Reload Value                                                 */
            uint32_t            : 16;
    } AR_b;
  } ;
  
  union {
    __IOM uint32_t CC;                          /*!< (@ 0x00000010) Timer Capture/Compare Register                             */
    
    struct {
      __IOM uint32_t CC         : 16;           /*!< [15..0] Capture/Compare Value                                             */
            uint32_t            : 16;
    } CC_b;
  } ;
  
  union {
    __IOM uint32_t IEN;                         /*!< (@ 0x00000014) Timer Interrupt Enable Register                            */
    
    struct {
      __IOM uint32_t UPD        : 1;            /*!< [0..0] Update Interrupt Enable                                            */
      __IOM uint32_t CMP        : 1;            /*!< [1..1] Compare Interrupt Enable                                           */
      __IOM uint32_t CAP        : 1;            /*!< [2..2] Capture Interrupt Enable                                           */
            uint32_t            : 5;
      __IOM uint32_t COF        : 1;            /*!< [8..8] Capture Overflow Interrupt Enable                                  */
            uint32_t            : 23;
    } IEN_b;
  } ;
  
  union {
    __IOM uint32_t IPND;                        /*!< (@ 0x00000018) Timer Interrupt Pending Register                           */
    
    struct {
      __IOM uint32_t UPD        : 1;            /*!< [0..0] Update Interrupt Pending                                           */
      __IOM uint32_t CMP        : 1;            /*!< [1..1] Compare Interrupt Pending                                          */
      __IOM uint32_t CAP        : 1;            /*!< [2..2] Capture Interrupt Pending                                          */
            uint32_t            : 5;
      __IOM uint32_t COF        : 1;            /*!< [8..8] Capture Overflow Interrupt Pending                                 */
            uint32_t            : 23;
    } IPND_b;
  } ;
  
  union {
    __IOM uint32_t EIPND;                       /*!< (@ 0x0000001C) Timer Enabled Interrupt Pending Register                   */
    
    struct {
      __IOM uint32_t UPD        : 1;            /*!< [0..0] Enabled Update Interrupt Pending                                   */
      __IOM uint32_t CMP        : 1;            /*!< [1..1] Enabled Compare Interrupt Pending                                  */
      __IOM uint32_t CAP        : 1;            /*!< [2..2] Enabled Capture Interrupt Pending                                  */
            uint32_t            : 5;
      __IOM uint32_t COF        : 1;            /*!< [8..8] Enabled Capture Overflow Interrupt Pending                         */
            uint32_t            : 23;
    } EIPND_b;
  } ;
} TIM_Type;                                     /*!< Size = 32 (0x20)                                                          */



/* =========================================================================================================================== */
/* ================                                          LINUART                                          ================ */
/* =========================================================================================================================== */


/**
  * @brief UART with LIN slave mode support (LINUART)
  */

typedef struct {                                /*!< (@ 0x40003000) LINUART Structure                                          */
  
  union {
    __IOM uint32_t CR;                          /*!< (@ 0x00000000) LINUART Control Register                                   */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] LINUART Enable                                                     */
      __IOM uint32_t TXRXEN     : 1;            /*!< [1..1] LINUART TX/RX Enable                                               */
      __IOM uint32_t AUTEN      : 1;            /*!< [2..2] Automatic Bit Rate Adjustment Enable                               */
      __IOM uint32_t LINEN      : 1;            /*!< [3..3] LIN Mode Enable                                                    */
      __IOM uint32_t ISTVEN     : 1;            /*!< [4..4] Inter Synch Timing Verification Enable                             */
            uint32_t            : 1;
      __IOM uint32_t RXDIS      : 1;            /*!< [6..6] Disconnect RX Input                                                */
      __IOM uint32_t TXMODE     : 1;            /*!< [7..7] Transmitter Mode                                                   */
      __IOM uint32_t STP        : 1;            /*!< [8..8] Stop Bits                                                          */
      __IOM uint32_t PAR        : 1;            /*!< [9..9] Parity                                                             */
      __IOM uint32_t PAREN      : 1;            /*!< [10..10] Parity Enable                                                    */
      __IOM uint32_t MSMP       : 1;            /*!< [11..11] Multi Sample                                                     */
      __IOM uint32_t TXFCV      : 4;            /*!< [15..12] TX FIFO Compare Value                                            */
      __IOM uint32_t RXFCV      : 4;            /*!< [19..16] RX FIFO Compare Value                                            */
            uint32_t            : 8;
      __IOM uint32_t TINV       : 1;            /*!< [28..28] Transmit Output Inverted                                         */
      __IOM uint32_t RINV       : 1;            /*!< [29..29] Receive Input Inverted                                           */
      __IOM uint32_t LLB        : 1;            /*!< [30..30] Local Loop Back                                                  */
            uint32_t            : 1;
    } CR_b;
  } ;
  
  union {
    __IOM uint32_t SR;                          /*!< (@ 0x00000004) LINUART Status Register                                    */
    
    struct {
      __IM  uint32_t TXFE       : 1;            /*!< [0..0] TX FIFO Empty                                                      */
      __IM  uint32_t TXFF       : 1;            /*!< [1..1] TX FIFO Full                                                       */
      __IM  uint32_t TXFC       : 1;            /*!< [2..2] TX FIFO Compare Value Reached                                      */
      __IM  uint32_t TXFO       : 1;            /*!< [3..3] TX FIFO Overflow                                                   */
      __IM  uint32_t RXFE       : 1;            /*!< [4..4] RX FIFO Empty                                                      */
      __IM  uint32_t RXFF       : 1;            /*!< [5..5] RX FIFO Full                                                       */
      __IM  uint32_t RXFC       : 1;            /*!< [6..6] RX FIFO Compare Value Reached                                      */
      __IM  uint32_t RXFO       : 1;            /*!< [7..7] RX FIFO Overflow                                                   */
      __IOM uint32_t BRK        : 1;            /*!< [8..8] Break Detection                                                    */
      __IM  uint32_t TBSY       : 1;            /*!< [9..9] Transmitter Busy                                                   */
      __IM  uint32_t RBSY       : 1;            /*!< [10..10] Receiver Busy                                                    */
            uint32_t            : 21;
    } SR_b;
  } ;
  
  union {
    __IOM uint32_t BL;                          /*!< (@ 0x00000008) LINUART Bit Length                                         */
    
    struct {
            uint32_t            : 3;
      __IOM uint32_t BLEN       : 13;           /*!< [15..3] Bit Length                                                        */
            uint32_t            : 16;
    } BL_b;
  } ;
  
  union {
    __IOM uint32_t TXF;                         /*!< (@ 0x0000000C) LINUART Transmit FIFO                                      */
    
    struct {
      __OM  uint32_t DATA       : 8;            /*!< [7..0] TX Data                                                            */
            uint32_t            : 24;
    } TXF_b;
  } ;
  
  union {
    __IOM uint32_t RXF;                         /*!< (@ 0x00000010) LINUART Receive FIFO                                       */
    
    struct {
      __IM  uint32_t DATA       : 8;            /*!< [7..0] RX Data                                                            */
            uint32_t            : 24;
    } RXF_b;
  } ;
  
  union {
    __IOM uint32_t TXFFILL;                     /*!< (@ 0x00000014) LINUART TX FIFO Fill Counter                               */
    
    struct {
      __IOM uint32_t FFILL      : 4;            /*!< [3..0] TX FIFO Fill Counter                                               */
            uint32_t            : 28;
    } TXFFILL_b;
  } ;
  
  union {
    __IOM uint32_t RXFFILL;                     /*!< (@ 0x00000018) LINUART RX FIFO Fill Counter                               */
    
    struct {
      __IOM uint32_t FFILL      : 4;            /*!< [3..0] RX FIFO Fill Counter                                               */
            uint32_t            : 28;
    } RXFFILL_b;
  } ;
  
  union {
    __IOM uint32_t TXD;                         /*!< (@ 0x0000001C) LINUART Transmit Shift Register                            */
    
    struct {
      __IOM uint32_t DATA       : 8;            /*!< [7..0] TX Data                                                            */
            uint32_t            : 24;
    } TXD_b;
  } ;
  
  union {
    __IM  uint32_t RXD;                         /*!< (@ 0x00000020) LINUART Receive Shift Register                             */
    
    struct {
      __IM  uint32_t DATA       : 8;            /*!< [7..0] RX Data                                                            */
            uint32_t            : 24;
    } RXD_b;
  } ;
  
  union {
    __IOM uint32_t IEN;                         /*!< (@ 0x00000024) LINUART Interrupt Enable Register                          */
    
    struct {
      __IOM uint32_t TX         : 1;            /*!< [0..0] Single Byte TX Interrupt Enable                                    */
      __IOM uint32_t TXFE       : 1;            /*!< [1..1] TX FIFO Empty Interrupt Enable                                     */
      __IOM uint32_t TXFC       : 1;            /*!< [2..2] TX FIFO Compare Interrupt Enable                                   */
      __IOM uint32_t TXFO       : 1;            /*!< [3..3] TX FIFO Overflow Interrupt Enable                                  */
      __IOM uint32_t RXFNE      : 1;            /*!< [4..4] RX FIFO Not Empty Interrupt Enable                                 */
      __IOM uint32_t RXFF       : 1;            /*!< [5..5] RX FIFO Full Interrupt Enable                                      */
      __IOM uint32_t RXFC       : 1;            /*!< [6..6] RX FIFO Compare Interrupt Enable                                   */
      __IOM uint32_t RXFO       : 1;            /*!< [7..7] RX FIFO Overflow Interrupt Enable                                  */
      __IOM uint32_t BRSY       : 1;            /*!< [8..8] Break/Synch Interrupt Enable                                       */
      __IOM uint32_t PAR        : 1;            /*!< [9..9] Parity Error Interrupt Enable                                      */
      __IOM uint32_t FRM        : 1;            /*!< [10..10] Form Error Interrupt Enable                                      */
      __IOM uint32_t TXERR      : 1;            /*!< [11..11] Transmit Error Interrupt Enable                                  */
      __IOM uint32_t TXEND      : 1;            /*!< [12..12] Transmit End Interrupt Enable                                    */
      __IOM uint32_t TXFCE      : 1;            /*!< [13..13] Transmit End and FIFO Compare Interrupt Enable                   */
            uint32_t            : 18;
    } IEN_b;
  } ;
  
  union {
    __IOM uint32_t IPND;                        /*!< (@ 0x00000028) LINUART Interrupt Pending Register                         */
    
    struct {
      __IOM uint32_t TX         : 1;            /*!< [0..0] Single Byte TX Interrupt Pending                                   */
      __IOM uint32_t TXFE       : 1;            /*!< [1..1] TX FIFO Empty Interrupt Pending                                    */
      __IOM uint32_t TXFC       : 1;            /*!< [2..2] TX FIFO Compare Interrupt Pending                                  */
      __IOM uint32_t TXFO       : 1;            /*!< [3..3] TX FIFO Overflow Interrupt Pending                                 */
      __IOM uint32_t RXFNE      : 1;            /*!< [4..4] RX FIFO Not Empty Interrupt Pending                                */
      __IOM uint32_t RXFF       : 1;            /*!< [5..5] RX FIFO Full Interrupt Pending                                     */
      __IOM uint32_t RXFC       : 1;            /*!< [6..6] RX FIFO Compare Interrupt Pending                                  */
      __IOM uint32_t RXFO       : 1;            /*!< [7..7] RX FIFO Overflow Interrupt Pending                                 */
      __IOM uint32_t BRSY       : 1;            /*!< [8..8] Break/Synch Interrupt Pending                                      */
      __IOM uint32_t PAR        : 1;            /*!< [9..9] Parity Error Interrupt Pending                                     */
      __IOM uint32_t FRM        : 1;            /*!< [10..10] Form Error Interrupt Pending                                     */
      __IOM uint32_t TXERR      : 1;            /*!< [11..11] Transmit Error Interrupt Pending                                 */
      __IOM uint32_t TXEND      : 1;            /*!< [12..12] Transmit End Interrupt Pending                                   */
      __IOM uint32_t TXFCE      : 1;            /*!< [13..13] Transmit End and FIFO Compare Interrupt Pending                  */
            uint32_t            : 18;
    } IPND_b;
  } ;
  
  union {
    __IOM uint32_t EIPND;                       /*!< (@ 0x0000002C) LINUART Enabled Interrupt Pending Register                 */
    
    struct {
      __IOM uint32_t TX         : 1;            /*!< [0..0] Enabled Single Byte TX Interrupt Pending                           */
      __IOM uint32_t TXFE       : 1;            /*!< [1..1] Enabled TX FIFO Empty Interrupt Pending                            */
      __IOM uint32_t TXFC       : 1;            /*!< [2..2] Enabled TX FIFO Compare Interrupt Pending                          */
      __IOM uint32_t TXFO       : 1;            /*!< [3..3] Enabled TX FIFO Overflow Interrupt Pending                         */
      __IOM uint32_t RXFNE      : 1;            /*!< [4..4] Enabled RX FIFO Not Empty Interrupt Pending                        */
      __IOM uint32_t RXFF       : 1;            /*!< [5..5] Enabled RX FIFO Full Interrupt Pending                             */
      __IOM uint32_t RXFC       : 1;            /*!< [6..6] Enabled RX FIFO Compare Interrupt Pending                          */
      __IOM uint32_t RXFO       : 1;            /*!< [7..7] Enabled RX FIFO Overflow Interrupt Pending                         */
      __IOM uint32_t BRSY       : 1;            /*!< [8..8] Enabled Break/Synch Interrupt Pending                              */
      __IOM uint32_t PAR        : 1;            /*!< [9..9] Enabled Parity Error Interrupt Pending                             */
      __IOM uint32_t FRM        : 1;            /*!< [10..10] Enabled Form Error Interrupt Pending                             */
      __IOM uint32_t TXERR      : 1;            /*!< [11..11] Enabled Transmit Error Interrupt Pending                         */
      __IOM uint32_t TXEND      : 1;            /*!< [12..12] Enabled Transmit End Interrupt Pending                           */
      __IOM uint32_t TXFCE      : 1;            /*!< [13..13] Enabled Transmit End and FIFO Compare Interrupt Pending          */
            uint32_t            : 18;
    } EIPND_b;
  } ;
} LINUART_Type;                                 /*!< Size = 48 (0x30)                                                          */



/* =========================================================================================================================== */
/* ================                                           EPWM                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief 3-channel PWM for bridge control (EPWM)
  */

typedef struct {                                /*!< (@ 0x40004000) EPWM Structure                                             */
  
  union {
    __IOM uint32_t CR0;                         /*!< (@ 0x00000000) EPWM Control Register 0                                    */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] EPWM Enable                                                        */
      __IOM uint32_t PAM        : 1;            /*!< [1..1] PWM Alignment Mode                                                 */
      __IOM uint32_t SR         : 1;            /*!< [2..2] Slew Rate                                                          */
      __IOM uint32_t OCSDM      : 1;            /*!< [3..3] Overcurrent Shutdown Mode                                          */
      __IOM uint32_t CCPT       : 4;            /*!< [7..4] Cross-Current Protection Time                                      */
      __IOM uint32_t CKSEL      : 3;            /*!< [10..8] Clock Selection                                                   */
            uint32_t            : 1;
      __IOM uint32_t OCFT       : 3;            /*!< [14..12] Overcurrent Filter Time                                          */
            uint32_t            : 1;
      __IOM uint32_t BEMFM      : 2;            /*!< [17..16] BEMF Comparator Mode                                             */
      __IOM uint32_t BCM        : 2;            /*!< [19..18] Bridge Control Mode                                              */
      __IOM uint32_t BLKTM      : 1;            /*!< [20..20] Blank Time Trigger Enable                                        */
            uint32_t            : 1;
      __IOM uint32_t HSOCDIS    : 1;            /*!< [22..22] Highside Overcurrent Disable                                     */
      __IOM uint32_t GM         : 1;            /*!< [23..23] Gate-Driver Mode                                                 */
            uint32_t            : 8;
    } CR0_b;
  } ;
  
  union {
    __IOM uint32_t CR1;                         /*!< (@ 0x00000004) EPWM Control Register 1                                    */
    
    struct {
      __IOM uint32_t LSOM0      : 2;            /*!< [1..0] EPWM Lowside Output Mode Halfbridge 0                              */
      __IOM uint32_t HSOM0      : 2;            /*!< [3..2] EPWM Highside Output Mode Halfbridge 0                             */
      __IOM uint32_t LSOM1      : 2;            /*!< [5..4] EPWM Lowside Output Mode Halfbridge 1                              */
      __IOM uint32_t HSOM1      : 2;            /*!< [7..6] EPWM Highside Output Mode Halfbridge 1                             */
      __IOM uint32_t LSOM2      : 2;            /*!< [9..8] EPWM Lowside Output Mode Halfbridge 2                              */
      __IOM uint32_t HSOM2      : 2;            /*!< [11..10] EPWM Highside Output Mode Halfbridge 2                           */
      __IOM uint32_t LSOM3      : 2;            /*!< [13..12] EPWM Lowside Output Mode Halfbridge 3                            */
      __IOM uint32_t HSOM3      : 2;            /*!< [15..14] EPWM Highside Output Mode Halfbridge 3                           */
      __IOM uint32_t INSEL0     : 2;            /*!< [17..16] PWM Input Select for Halfbridge 0                                */
      __IOM uint32_t INSEL1     : 2;            /*!< [19..18] PWM Input Select for Halfbridge 1                                */
      __IOM uint32_t INSEL2     : 2;            /*!< [21..20] PWM Input Select for Halfbridge 2                                */
      __IOM uint32_t INSEL3     : 2;            /*!< [23..22] PWM Input Select for Halfbridge 3                                */
      __IOM uint32_t BEMFSEL    : 2;            /*!< [25..24] BEMF Mode Comparator Input Select                                */
      __IOM uint32_t PWM2M      : 2;            /*!< [27..26] PWM2 Counter Mode                                                */
      __IOM uint32_t CLM0       : 1;            /*!< [28..28] EPWM0 Current Limit Mode                                         */
      __IOM uint32_t CLM1       : 1;            /*!< [29..29] EPWM1 Current Limit Mode                                         */
      __IOM uint32_t CLM2       : 1;            /*!< [30..30] EPWM2 Current Limit Mode                                         */
      __IOM uint32_t CLMIM      : 1;            /*!< [31..31] Current Limit Input Mode                                         */
    } CR1_b;
  } ;
  
  union {
    __IOM uint32_t CR2;                         /*!< (@ 0x00000008) EPWM Control Register 2                                    */
    
    struct {
      __IOM uint32_t PRBE0      : 1;            /*!< [0..0] EPWM0 Register Buffer Enable                                       */
      __IOM uint32_t PRBE1      : 1;            /*!< [1..1] EPWM1 Register Buffer Enable                                       */
      __IOM uint32_t PRBE2      : 1;            /*!< [2..2] EPWM2 Register Buffer Enable                                       */
            uint32_t            : 1;
      __IOM uint32_t PRUM0      : 1;            /*!< [4..4] EPWM0 Register Update Mode                                         */
      __IOM uint32_t PRUM1      : 1;            /*!< [5..5] EPWM1 Register Update Mode                                         */
      __IOM uint32_t PRUM2      : 1;            /*!< [6..6] EPWM2 Register Update Mode                                         */
            uint32_t            : 1;
      __IOM uint32_t PUR0       : 1;            /*!< [8..8] EPWM0 Register Update Request                                      */
      __IOM uint32_t PUR1       : 1;            /*!< [9..9] EPWM1 Register Update Request                                      */
      __IOM uint32_t PUR2       : 1;            /*!< [10..10] EPWM2 Register Update Request                                    */
            uint32_t            : 5;
      __IOM uint32_t CLBE       : 1;            /*!< [16..16] CLDAC Register Buffer Enable                                     */
      __IOM uint32_t CLUEOP     : 1;            /*!< [17..17] CLDAC Register Update on EOP                                     */
      __IOM uint32_t CLUTRG     : 1;            /*!< [18..18] CLDAC Register Update on TRG                                     */
            uint32_t            : 5;
      __IOM uint32_t CR1BE      : 1;            /*!< [24..24] CR1 Register Buffer Enable                                       */
      __IOM uint32_t CR1UEOP    : 1;            /*!< [25..25] CR1 Register Update on EOP                                       */
      __IOM uint32_t CR1UTRG    : 1;            /*!< [26..26] CR1 Register Update on TRG                                       */
            uint32_t            : 5;
    } CR2_b;
  } ;
  
  union {
    __IOM uint32_t TCR;                         /*!< (@ 0x0000000C) EPWM Trigger Control Register                              */
    
    struct {
      __IOM uint32_t DEC0       : 4;            /*!< [3..0] EPWM Channel 0 Trigger Decimation                                  */
      __IOM uint32_t UCE0       : 1;            /*!< [4..4] EPWM Channel 0 Up-Counting Trigger Enable                          */
      __IOM uint32_t DCE0       : 1;            /*!< [5..5] EPWM Channel 0 Down-Counting Trigger Enable                        */
            uint32_t            : 2;
      __IOM uint32_t DEC1       : 4;            /*!< [11..8] EPWM Channel 1 Trigger Decimation                                 */
      __IOM uint32_t UCE1       : 1;            /*!< [12..12] EPWM Channel 1 Up-Counting Trigger Enable                        */
      __IOM uint32_t DCE1       : 1;            /*!< [13..13] EPWM Channel 1 Down-Counting Trigger Enable                      */
            uint32_t            : 2;
      __IOM uint32_t DEC2       : 4;            /*!< [19..16] EPWM Channel 2 Trigger Decimation                                */
      __IOM uint32_t UCE2       : 1;            /*!< [20..20] EPWM Channel 2 Up-Counting Trigger Enable                        */
      __IOM uint32_t DCE2       : 1;            /*!< [21..21] EPWM Channel 2 Down-Counting Trigger Enable                      */
            uint32_t            : 10;
    } TCR_b;
  } ;
  
  union {
    __IOM uint32_t PER0;                        /*!< (@ 0x00000010) EPWM Channel 0 Period Register                             */
    
    struct {
      __IOM uint32_t PER        : 12;           /*!< [11..0] Period Value                                                      */
            uint32_t            : 20;
    } PER0_b;
  } ;
  
  union {
    __IOM uint32_t PER1;                        /*!< (@ 0x00000014) EPWM Channel 1 Period Register                             */
    
    struct {
      __IOM uint32_t PER        : 12;           /*!< [11..0] Period Value                                                      */
            uint32_t            : 20;
    } PER1_b;
  } ;
  
  union {
    __IOM uint32_t PER2;                        /*!< (@ 0x00000018) EPWM Channel 2 Period Register                             */
    
    struct {
      __IOM uint32_t PER        : 12;           /*!< [11..0] Period Value                                                      */
            uint32_t            : 20;
    } PER2_b;
  } ;
  
  union {
    __IOM uint32_t COMP0;                       /*!< (@ 0x0000001C) EPWM Channel 0 Compare Register                            */
    
    struct {
      __IOM uint32_t COMP       : 12;           /*!< [11..0] Compare Value                                                     */
            uint32_t            : 20;
    } COMP0_b;
  } ;
  
  union {
    __IOM uint32_t COMP1;                       /*!< (@ 0x00000020) EPWM Channel 1 Compare Register                            */
    
    struct {
      __IOM uint32_t COMP       : 12;           /*!< [11..0] Compare Value                                                     */
            uint32_t            : 20;
    } COMP1_b;
  } ;
  
  union {
    __IOM uint32_t COMP2;                       /*!< (@ 0x00000024) EPWM Channel 2 Compare Register                            */
    
    struct {
      __IOM uint32_t COMP       : 12;           /*!< [11..0] Compare Value                                                     */
            uint32_t            : 20;
    } COMP2_b;
  } ;
  
  union {
    __IM  uint32_t CAP0;                        /*!< (@ 0x00000028) EPWM Channel 0 Capture Register                            */
    
    struct {
      __IM  uint32_t CAP        : 12;           /*!< [11..0] Capture Value                                                     */
      __IM  uint32_t CDIR       : 1;            /*!< [12..12] Counter Direction                                                */
            uint32_t            : 3;
      __IM  uint32_t CAPU       : 12;           /*!< [27..16] Unbuffered Capture Value                                         */
      __IM  uint32_t CDIRU      : 1;            /*!< [28..28] Unbuffered Counter Direction                                     */
            uint32_t            : 3;
    } CAP0_b;
  } ;
  
  union {
    __IM  uint32_t CAP1;                        /*!< (@ 0x0000002C) EPWM Channel 1 Capture Register                            */
    
    struct {
      __IM  uint32_t CAP        : 12;           /*!< [11..0] Capture Value                                                     */
      __IM  uint32_t CDIR       : 1;            /*!< [12..12] Counter Direction                                                */
            uint32_t            : 3;
      __IM  uint32_t CAPU       : 12;           /*!< [27..16] Unbuffered Capture Value                                         */
      __IM  uint32_t CDIRU      : 1;            /*!< [28..28] Unbuffered Counter Direction                                     */
            uint32_t            : 3;
    } CAP1_b;
  } ;
  
  union {
    __IM  uint32_t CAP2;                        /*!< (@ 0x00000030) EPWM Channel 2 Capture Register                            */
    
    struct {
      __IM  uint32_t CAP        : 12;           /*!< [11..0] Capture Value                                                     */
      __IM  uint32_t CDIR       : 1;            /*!< [12..12] Counter Direction                                                */
            uint32_t            : 3;
      __IM  uint32_t CAPU       : 12;           /*!< [27..16] Unbuffered Capture Value                                         */
      __IM  uint32_t CDIRU      : 1;            /*!< [28..28] Unbuffered Counter Direction                                     */
            uint32_t            : 3;
    } CAP2_b;
  } ;
  
  union {
    __IOM uint32_t TRG0;                        /*!< (@ 0x00000034) EPWM Channel 0 Trigger Register                            */
    
    struct {
      __IOM uint32_t TRG        : 12;           /*!< [11..0] Trigger Value                                                     */
            uint32_t            : 20;
    } TRG0_b;
  } ;
  
  union {
    __IOM uint32_t TRG1;                        /*!< (@ 0x00000038) EPWM Channel 1 Trigger Register                            */
    
    struct {
      __IOM uint32_t TRG        : 12;           /*!< [11..0] Trigger Value                                                     */
            uint32_t            : 20;
    } TRG1_b;
  } ;
  
  union {
    __IOM uint32_t TRG2;                        /*!< (@ 0x0000003C) EPWM Channel 2 Trigger Register                            */
    
    struct {
      __IOM uint32_t TRG        : 12;           /*!< [11..0] Trigger Value                                                     */
            uint32_t            : 20;
    } TRG2_b;
  } ;
  
  union {
    __IOM uint32_t CLDAC;                       /*!< (@ 0x00000040) Current Limit DAC Register                                 */
    
    struct {
      __IOM uint32_t DATA0      : 8;            /*!< [7..0] Current Limit DAC 0 Data                                           */
      __IOM uint32_t BLT0       : 1;            /*!< [8..8] DAC 0 Blank Time Trigger                                           */
            uint32_t            : 7;
      __IOM uint32_t DATA1      : 8;            /*!< [23..16] Current Limit DAC 1 Data                                         */
      __IOM uint32_t BLT1       : 1;            /*!< [24..24] DAC 1 Blank Time Trigger                                         */
            uint32_t            : 7;
    } CLDAC_b;
  } ;
  
  union {
    __IM  uint32_t CLDACC;                      /*!< (@ 0x00000044) CLDAC Coefficients Register                                */
    
    struct {
      __IM  uint32_t OCORR0     : 5;            /*!< [4..0] CLDAC0 Offset Correction                                           */
            uint32_t            : 3;
      __IM  uint32_t GCORR0     : 8;            /*!< [15..8] CLDAC0 Gain Correction                                            */
      __IM  uint32_t OCORR1     : 5;            /*!< [20..16] CLDAC1 Offset Correction                                         */
            uint32_t            : 3;
      __IM  uint32_t GCORR1     : 8;            /*!< [31..24] CLDAC1 Gain Correction                                           */
    } CLDACC_b;
  } ;
  
  union {
    __IOM uint32_t OC;                          /*!< (@ 0x00000048) EPWM Overcurrent Register                                  */
    
    struct {
      __IOM uint32_t LSOC0      : 1;            /*!< [0..0] Lowside Overcurrent MOUT0                                          */
      __IOM uint32_t LSOC1      : 1;            /*!< [1..1] Lowside Overcurrent MOUT1                                          */
      __IOM uint32_t LSOC2      : 1;            /*!< [2..2] Lowside Overcurrent MOUT2                                          */
      __IOM uint32_t LSOC3      : 1;            /*!< [3..3] Lowside Overcurrent MOUT3                                          */
            uint32_t            : 4;
      __IOM uint32_t HSOC0      : 1;            /*!< [8..8] Highside Overcurrent MOUT0                                         */
      __IOM uint32_t HSOC1      : 1;            /*!< [9..9] Highside Overcurrent MOUT1                                         */
      __IOM uint32_t HSOC2      : 1;            /*!< [10..10] Highside Overcurrent MOUT2                                       */
      __IOM uint32_t HSOC3      : 1;            /*!< [11..11] Highside Overcurrent MOUT3                                       */
            uint32_t            : 20;
    } OC_b;
  } ;
  
  union {
    __IOM uint32_t MOT;                         /*!< (@ 0x0000004C) Minimum On Time Register                                   */
    
    struct {
      __IOM uint32_t MOT        : 12;           /*!< [11..0] Minimum On Time                                                   */
            uint32_t            : 4;
      __IOM uint32_t MEN0       : 1;            /*!< [16..16] Channel 0 Minimum On Time Enable                                 */
      __IOM uint32_t MEN1       : 1;            /*!< [17..17] Channel 1 Minimum On Time Enable                                 */
      __IOM uint32_t MEN2       : 1;            /*!< [18..18] Channel 2 Minimum On Time Enable                                 */
            uint32_t            : 13;
    } MOT_b;
  } ;
  
  union {
    __IOM uint32_t IEN;                         /*!< (@ 0x00000050) Timer Interrupt Enable Register                            */
    
    struct {
      __IOM uint32_t EOP0       : 1;            /*!< [0..0] Channel 0 End Of Period Interrupt Enable                           */
      __IOM uint32_t CMP0       : 1;            /*!< [1..1] Channel 0 Compare Interrupt Enable                                 */
      __IOM uint32_t CAP0       : 1;            /*!< [2..2] Channel 0 Capture Interrupt Enable                                 */
      __IOM uint32_t TRG0       : 1;            /*!< [3..3] Channel 0 Trigger Interrupt Enable                                 */
            uint32_t            : 4;
      __IOM uint32_t EOP1       : 1;            /*!< [8..8] Channel 1 End Of Period Interrupt Enable                           */
      __IOM uint32_t CMP1       : 1;            /*!< [9..9] Channel 1 Compare Interrupt Enable                                 */
      __IOM uint32_t CAP1       : 1;            /*!< [10..10] Channel 1 Capture Interrupt Enable                               */
      __IOM uint32_t TRG1       : 1;            /*!< [11..11] Channel 1 Trigger Interrupt Enable                               */
            uint32_t            : 4;
      __IOM uint32_t EOP2       : 1;            /*!< [16..16] Channel 2 End Of Period Interrupt Enable                         */
      __IOM uint32_t CMP2       : 1;            /*!< [17..17] Channel 2 Compare Interrupt Enable                               */
      __IOM uint32_t CAP2       : 1;            /*!< [18..18] Channel 2 Capture Interrupt Enable                               */
      __IOM uint32_t TRG2       : 1;            /*!< [19..19] Channel 2 Trigger Interrupt Enable                               */
            uint32_t            : 4;
      __IOM uint32_t OC         : 1;            /*!< [24..24] Overcurrent Interrupt Enable                                     */
            uint32_t            : 7;
    } IEN_b;
  } ;
  
  union {
    __IOM uint32_t IPND;                        /*!< (@ 0x00000054) Timer Interrupt Pending Register                           */
    
    struct {
      __IOM uint32_t EOP0       : 1;            /*!< [0..0] Channel 0 End Of Period Interrupt Pending                          */
      __IOM uint32_t CMP0       : 1;            /*!< [1..1] Channel 0 Compare Interrupt Pending                                */
      __IOM uint32_t CAP0       : 1;            /*!< [2..2] Channel 0 Capture Interrupt Pending                                */
      __IOM uint32_t TRG0       : 1;            /*!< [3..3] Channel 0 Trigger Interrupt Pending                                */
            uint32_t            : 4;
      __IOM uint32_t EOP1       : 1;            /*!< [8..8] Channel 1 End Of Period Interrupt Pending                          */
      __IOM uint32_t CMP1       : 1;            /*!< [9..9] Channel 1 Compare Interrupt Pending                                */
      __IOM uint32_t CAP1       : 1;            /*!< [10..10] Channel 1 Capture Interrupt Pending                              */
      __IOM uint32_t TRG1       : 1;            /*!< [11..11] Channel 1 Trigger Interrupt Pending                              */
            uint32_t            : 4;
      __IOM uint32_t EOP2       : 1;            /*!< [16..16] Channel 2 End Of Period Interrupt Pending                        */
      __IOM uint32_t CMP2       : 1;            /*!< [17..17] Channel 2 Compare Interrupt Pending                              */
      __IOM uint32_t CAP2       : 1;            /*!< [18..18] Channel 2 Capture Interrupt Pending                              */
      __IOM uint32_t TRG2       : 1;            /*!< [19..19] Channel 2 Trigger Interrupt Pending                              */
            uint32_t            : 4;
      __IOM uint32_t OC         : 1;            /*!< [24..24] Overcurrent Interrupt Pending                                    */
            uint32_t            : 7;
    } IPND_b;
  } ;
  
  union {
    __IOM uint32_t EIPND;                       /*!< (@ 0x00000058) Timer Enabled Interrupt Pending Register                   */
    
    struct {
      __IOM uint32_t EOP0       : 1;            /*!< [0..0] Channel 0 Enabled End Of Period Interrupt Pending                  */
      __IOM uint32_t CMP0       : 1;            /*!< [1..1] Channel 0 Enabled Compare Interrupt Pending                        */
      __IOM uint32_t CAP0       : 1;            /*!< [2..2] Channel 0 Enabled Capture Interrupt Pending                        */
      __IOM uint32_t TRG0       : 1;            /*!< [3..3] Channel 0 Enabled Trigger Interrupt Pending                        */
            uint32_t            : 4;
      __IOM uint32_t EOP1       : 1;            /*!< [8..8] Channel 1 Enabled End Of Period Interrupt Pending                  */
      __IOM uint32_t CMP1       : 1;            /*!< [9..9] Channel 1 Enabled Compare Interrupt Pending                        */
      __IOM uint32_t CAP1       : 1;            /*!< [10..10] Channel 1 Enabled Capture Interrupt Pending                      */
      __IOM uint32_t TRG1       : 1;            /*!< [11..11] Channel 1 Enabled Trigger Interrupt Pending                      */
            uint32_t            : 4;
      __IOM uint32_t EOP2       : 1;            /*!< [16..16] Channel 2 Enabled End Of Period Interrupt Pending                */
      __IOM uint32_t CMP2       : 1;            /*!< [17..17] Channel 2 Enabled Compare Interrupt Pending                      */
      __IOM uint32_t CAP2       : 1;            /*!< [18..18] Channel 2 Enabled Capture Interrupt Pending                      */
      __IOM uint32_t TRG2       : 1;            /*!< [19..19] Channel 2 Enabled Trigger Interrupt Pending                      */
            uint32_t            : 4;
      __IOM uint32_t OC         : 1;            /*!< [24..24] Enabled Overcurrent Interrupt Pending                            */
            uint32_t            : 7;
    } EIPND_b;
  } ;
} EPWM_Type;                                    /*!< Size = 92 (0x5c)                                                          */



/* =========================================================================================================================== */
/* ================                                          CAPCOM                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief 3-Channel Capture/Compare Unit (CAPCOM)
  */

typedef struct {                                /*!< (@ 0x40005000) CAPCOM Structure                                           */
  
  union {
    __IOM uint32_t CR;                          /*!< (@ 0x00000000) CAPCOM Control Register                                    */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] CAPCOM Enable                                                      */
      __IOM uint32_t RBE        : 1;            /*!< [1..1] Register Buffer Enable                                             */
            uint32_t            : 1;
      __IOM uint32_t ACM        : 1;            /*!< [3..3] Advanced Capture Mode                                              */
            uint32_t            : 4;
      __IOM uint32_t IAM0       : 2;            /*!< [9..8] Channel 0 Input Action Mode                                        */
      __IOM uint32_t OAM0       : 2;            /*!< [11..10] Channel 0 Output Action Mode                                     */
      __IOM uint32_t CIF0       : 3;            /*!< [14..12] Channel 0 Capture Input Filter                                   */
      __IOM uint32_t CIS0       : 1;            /*!< [15..15] Channel 0 Capture Input Select                                   */
      __IOM uint32_t IAM1       : 2;            /*!< [17..16] Channel 1 Input Action Mode                                      */
      __IOM uint32_t OAM1       : 2;            /*!< [19..18] Channel 1 Output Action Mode                                     */
      __IOM uint32_t CIF1       : 3;            /*!< [22..20] Channel 1 Capture Input Filter                                   */
      __IOM uint32_t CIS1       : 1;            /*!< [23..23] Channel 1 Capture Input Select                                   */
      __IOM uint32_t IAM2       : 2;            /*!< [25..24] Channel 2 Input Action Mode                                      */
      __IOM uint32_t OAM2       : 2;            /*!< [27..26] Channel 2 Output Action Mode                                     */
      __IOM uint32_t CIF2       : 3;            /*!< [30..28] Channel 2 Capture Input Filter                                   */
      __IOM uint32_t CIS2       : 1;            /*!< [31..31] Channel 2 Capture Input Select                                   */
    } CR_b;
  } ;
  
  union {
    __IM  uint32_t CNT;                         /*!< (@ 0x00000004) CAPCOM Counter Register                                    */
    
    struct {
      __IM  uint32_t CNT        : 16;           /*!< [15..0] Counter Value                                                     */
            uint32_t            : 16;
    } CNT_b;
  } ;
  
  union {
    __IOM uint32_t PS;                          /*!< (@ 0x00000008) CAPCOM Prescaler Register                                  */
    
    struct {
      __IOM uint32_t PS         : 16;           /*!< [15..0] Prescaler Value                                                   */
            uint32_t            : 16;
    } PS_b;
  } ;
  
  union {
    __IOM uint32_t CAP0;                        /*!< (@ 0x0000000C) CAPCOM Channel 0 Capture Register                          */
    
    struct {
      __IOM uint32_t CAP        : 16;           /*!< [15..0] Capture Value                                                     */
            uint32_t            : 16;
    } CAP0_b;
  } ;
  
  union {
    __IOM uint32_t CAP1;                        /*!< (@ 0x00000010) CAPCOM Channel 1 Capture Register                          */
    
    struct {
      __IOM uint32_t CAP        : 16;           /*!< [15..0] Capture Value                                                     */
            uint32_t            : 16;
    } CAP1_b;
  } ;
  
  union {
    __IOM uint32_t CAP2;                        /*!< (@ 0x00000014) CAPCOM Channel 2 Capture Register                          */
    
    struct {
      __IOM uint32_t CAP        : 16;           /*!< [15..0] Capture Value                                                     */
            uint32_t            : 16;
    } CAP2_b;
  } ;
  
  union {
    __IOM uint32_t COMP0;                       /*!< (@ 0x00000018) CAPCOM Channel 0 Compare Register                          */
    
    struct {
      __IOM uint32_t COMP       : 16;           /*!< [15..0] Compare Value                                                     */
            uint32_t            : 16;
    } COMP0_b;
  } ;
  
  union {
    __IOM uint32_t COMP1;                       /*!< (@ 0x0000001C) CAPCOM Channel 1 Compare Register                          */
    
    struct {
      __IOM uint32_t COMP       : 16;           /*!< [15..0] Compare Value                                                     */
            uint32_t            : 16;
    } COMP1_b;
  } ;
  
  union {
    __IOM uint32_t COMP2;                       /*!< (@ 0x00000020) CAPCOM Channel 2 Compare Register                          */
    
    struct {
      __IOM uint32_t COMP       : 16;           /*!< [15..0] Compare Value                                                     */
            uint32_t            : 16;
    } COMP2_b;
  } ;
  
  union {
    __IOM uint32_t REFP;                        /*!< (@ 0x00000024) CAPCOM Reference Pattern                                   */
    
    struct {
      __IOM uint32_t REFP       : 3;            /*!< [2..0] Reference input pattern                                            */
            uint32_t            : 29;
    } REFP_b;
  } ;
  
  union {
    __IOM uint32_t IEN;                         /*!< (@ 0x00000028) CAPCOM Interrupt Enable Register                           */
    
    struct {
      __IOM uint32_t OVF0       : 1;            /*!< [0..0] Channel 0 Overflow Interrupt Enable                                */
      __IOM uint32_t CMP0       : 1;            /*!< [1..1] Channel 0 Compare Interrupt Enable                                 */
      __IOM uint32_t CAP0       : 1;            /*!< [2..2] Channel 0 Capture Interrupt Enable                                 */
      __IOM uint32_t CAOF0      : 1;            /*!< [3..3] Channel 0 Capture Overflow Interrupt Enable                        */
      __IOM uint32_t OVF1       : 1;            /*!< [4..4] Channel 1 Overflow Interrupt Enable                                */
      __IOM uint32_t CMP1       : 1;            /*!< [5..5] Channel 1 Compare Interrupt Enable                                 */
      __IOM uint32_t CAP1       : 1;            /*!< [6..6] Channel 1 Capture Interrupt Enable                                 */
      __IOM uint32_t CAOF1      : 1;            /*!< [7..7] Channel 1 Capture Overflow Interrupt Enable                        */
      __IOM uint32_t OVF2       : 1;            /*!< [8..8] Channel 2 Overflow Interrupt Enable                                */
      __IOM uint32_t CMP2       : 1;            /*!< [9..9] Channel 2 Compare Interrupt Enable                                 */
      __IOM uint32_t CAP2       : 1;            /*!< [10..10] Channel 2 Capture Interrupt Enable                               */
      __IOM uint32_t CAOF2      : 1;            /*!< [11..11] Channel 2 Capture Overflow Interrupt Enable                      */
      __IOM uint32_t RP         : 1;            /*!< [12..12] Right Pattern Interrupt Enable                                   */
      __IOM uint32_t WP         : 1;            /*!< [13..13] Wrong Pattern Interrupt Enable                                   */
            uint32_t            : 18;
    } IEN_b;
  } ;
  
  union {
    __IOM uint32_t IPND;                        /*!< (@ 0x0000002C) CAPCOM Interrupt Pending Register                          */
    
    struct {
      __IOM uint32_t OVF0       : 1;            /*!< [0..0] Channel 0 Overflow Interrupt Pending                               */
      __IOM uint32_t CMP0       : 1;            /*!< [1..1] Channel 0 Compare Interrupt Pending                                */
      __IOM uint32_t CAP0       : 1;            /*!< [2..2] Channel 0 Capture Interrupt Pending                                */
      __IOM uint32_t CAOF0      : 1;            /*!< [3..3] Channel 0 Capture Overflow Interrupt Pending                       */
      __IOM uint32_t OVF1       : 1;            /*!< [4..4] Channel 1 Overflow Interrupt Pending                               */
      __IOM uint32_t CMP1       : 1;            /*!< [5..5] Channel 1 Compare Interrupt Pending                                */
      __IOM uint32_t CAP1       : 1;            /*!< [6..6] Channel 1 Capture Interrupt Pending                                */
      __IOM uint32_t CAOF1      : 1;            /*!< [7..7] Channel 1 Capture Overflow Interrupt Pending                       */
      __IOM uint32_t OVF2       : 1;            /*!< [8..8] Channel 2 Overflow Interrupt Pending                               */
      __IOM uint32_t CMP2       : 1;            /*!< [9..9] Channel 2 Compare Interrupt Pending                                */
      __IOM uint32_t CAP2       : 1;            /*!< [10..10] Channel 2 Capture Interrupt Pending                              */
      __IOM uint32_t CAOF2      : 1;            /*!< [11..11] Channel 2 Capture Overflow Interrupt Pending                     */
      __IOM uint32_t RP         : 1;            /*!< [12..12] Right Pattern Interrupt Pending                                  */
      __IOM uint32_t WP         : 1;            /*!< [13..13] Wrong Pattern Interrupt Pending                                  */
            uint32_t            : 18;
    } IPND_b;
  } ;
  
  union {
    __IOM uint32_t EIPND;                       /*!< (@ 0x00000030) CAPCOM Enabled Interrupt Pending Register                  */
    
    struct {
      __IOM uint32_t OVF0       : 1;            /*!< [0..0] Channel 0 Enabled Overflow Interrupt Pending                       */
      __IOM uint32_t CMP0       : 1;            /*!< [1..1] Channel 0 Enabled Compare Interrupt Pending                        */
      __IOM uint32_t CAP0       : 1;            /*!< [2..2] Channel 0 Enabled Capture Interrupt Pending                        */
      __IOM uint32_t CAOF0      : 1;            /*!< [3..3] Channel 0 Enabled Capture Overflow Interrupt Pending               */
      __IOM uint32_t OVF1       : 1;            /*!< [4..4] Channel 1 Enabled Overflow Interrupt Pending                       */
      __IOM uint32_t CMP1       : 1;            /*!< [5..5] Channel 1 Enabled Compare Interrupt Pending                        */
      __IOM uint32_t CAP1       : 1;            /*!< [6..6] Channel 1 Enabled Capture Interrupt Pending                        */
      __IOM uint32_t CAOF1      : 1;            /*!< [7..7] Channel 1 Enabled Capture Overflow Interrupt Pending               */
      __IOM uint32_t OVF2       : 1;            /*!< [8..8] Channel 2 Enabled Overflow Interrupt Pending                       */
      __IOM uint32_t CMP2       : 1;            /*!< [9..9] Channel 2 Enabled Compare Interrupt Pending                        */
      __IOM uint32_t CAP2       : 1;            /*!< [10..10] Channel 2 Enabled Capture Interrupt Pending                      */
      __IOM uint32_t CAOF2      : 1;            /*!< [11..11] Channel 2 Enabled Capture Overflow Interrupt Pending             */
      __IOM uint32_t RP         : 1;            /*!< [12..12] Enabled Right Pattern Interrupt Pending                          */
      __IOM uint32_t WP         : 1;            /*!< [13..13] Enabled Wrong Pattern Interrupt Pending                          */
            uint32_t            : 18;
    } EIPND_b;
  } ;
} CAPCOM_Type;                                  /*!< Size = 52 (0x34)                                                          */



/* =========================================================================================================================== */
/* ================                                            ADC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Analog to Digital Converter (ADC)
  */

typedef struct {                                /*!< (@ 0x40006000) ADC Structure                                              */
  
  union {
    __IOM uint32_t CR;                          /*!< (@ 0x00000000) ADC Control Register                                       */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] ADC Enable                                                         */
      __IOM uint32_t TTEN       : 1;            /*!< [1..1] Trigger Timer Enable                                               */
      __IOM uint32_t HPSWT      : 1;            /*!< [2..2] HP Queue Software Trigger                                          */
      __IOM uint32_t LPSWT      : 1;            /*!< [3..3] LP Queue Software Trigger                                          */
      __IOM uint32_t NHP        : 3;            /*!< [6..4] HP Queue Length                                                    */
            uint32_t            : 1;
      __IOM uint32_t HPTS       : 3;            /*!< [10..8] HP Queue Trigger Source                                           */
            uint32_t            : 1;
      __IOM uint32_t LPTS       : 3;            /*!< [14..12] LP Queue Trigger Source                                          */
            uint32_t            : 1;
      __IM  uint32_t BUSY       : 1;            /*!< [16..16] ADC Busy                                                         */
            uint32_t            : 15;
    } CR_b;
  } ;
  
  union {
    __IOM uint32_t TTP;                         /*!< (@ 0x00000004) ADC Trigger Timer Period                                   */
    
    struct {
      __IOM uint32_t TPER       : 12;           /*!< [11..0] Trigger Timer Period                                              */
            uint32_t            : 20;
    } TTP_b;
  } ;
  
  union {
    __IOM uint32_t QCR1;                        /*!< (@ 0x00000008) ADC Queue Control Register 1                               */
    
    struct {
      __IOM uint32_t Q0SEL      : 5;            /*!< [4..0] Queue Entry 0 Source Selection                                     */
      __IOM uint32_t Q0G        : 3;            /*!< [7..5] Queue Entry 0 PGA Gain                                             */
      __IOM uint32_t Q1SEL      : 5;            /*!< [12..8] Queue Entry 1 Source Selection                                    */
      __IOM uint32_t Q1G        : 3;            /*!< [15..13] Queue Entry 1 PGA Gain                                           */
      __IOM uint32_t Q2SEL      : 5;            /*!< [20..16] Queue Entry 2 Source Selection                                   */
      __IOM uint32_t Q2G        : 3;            /*!< [23..21] Queue Entry 2 PGA Gain                                           */
      __IOM uint32_t Q3SEL      : 5;            /*!< [28..24] Queue Entry 3 Source Selection                                   */
      __IOM uint32_t Q3G        : 3;            /*!< [31..29] Queue Entry 3 PGA Gain                                           */
    } QCR1_b;
  } ;
  
  union {
    __IOM uint32_t QCR2;                        /*!< (@ 0x0000000C) ADC Queue Control Register 2                               */
    
    struct {
      __IOM uint32_t Q4SEL      : 5;            /*!< [4..0] Queue Entry 4 Source Selection                                     */
      __IOM uint32_t Q4G        : 3;            /*!< [7..5] Queue Entry 4 PGA Gain                                             */
      __IOM uint32_t Q5SEL      : 5;            /*!< [12..8] Queue Entry 5 Source Selection                                    */
      __IOM uint32_t Q5G        : 3;            /*!< [15..13] Queue Entry 5 PGA Gain                                           */
      __IOM uint32_t Q6SEL      : 5;            /*!< [20..16] Queue Entry 6 Source Selection                                   */
      __IOM uint32_t Q6G        : 3;            /*!< [23..21] Queue Entry 6 PGA Gain                                           */
      __IOM uint32_t Q7SEL      : 5;            /*!< [28..24] Queue Entry 7 Source Selection                                   */
      __IOM uint32_t Q7G        : 3;            /*!< [31..29] Queue Entry 7 PGA Gain                                           */
    } QCR2_b;
  } ;
  
  union {
    __IOM uint32_t DR0;                         /*!< (@ 0x00000010) ADC Data 0 Register                                        */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Data                                                              */
            uint32_t            : 16;
    } DR0_b;
  } ;
  
  union {
    __IOM uint32_t DR1;                         /*!< (@ 0x00000014) ADC Data 1 Register                                        */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Data                                                              */
            uint32_t            : 16;
    } DR1_b;
  } ;
  
  union {
    __IOM uint32_t DR2;                         /*!< (@ 0x00000018) ADC Data 2 Register                                        */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Data                                                              */
            uint32_t            : 16;
    } DR2_b;
  } ;
  
  union {
    __IOM uint32_t DR3;                         /*!< (@ 0x0000001C) ADC Data 3 Register                                        */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Data                                                              */
            uint32_t            : 16;
    } DR3_b;
  } ;
  
  union {
    __IOM uint32_t DR4;                         /*!< (@ 0x00000020) ADC Data 4 Register                                        */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Data                                                              */
            uint32_t            : 16;
    } DR4_b;
  } ;
  
  union {
    __IOM uint32_t DR5;                         /*!< (@ 0x00000024) ADC Data 5 Register                                        */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Data                                                              */
            uint32_t            : 16;
    } DR5_b;
  } ;
  
  union {
    __IOM uint32_t DR6;                         /*!< (@ 0x00000028) ADC Data 6 Register                                        */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Data                                                              */
            uint32_t            : 16;
    } DR6_b;
  } ;
  
  union {
    __IOM uint32_t DR7;                         /*!< (@ 0x0000002C) ADC Data 7 Register                                        */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Data                                                              */
            uint32_t            : 16;
    } DR7_b;
  } ;
  
  union {
    __IOM uint32_t IEN;                         /*!< (@ 0x00000030) ADC Interrupt Enable Register                              */
    
    struct {
      __IOM uint32_t HPEOC      : 1;            /*!< [0..0] End Of HP Conversion Interrupt Enable                              */
      __IOM uint32_t HPCOL      : 1;            /*!< [1..1] HP Trigger Collision Interrupt Enable                              */
            uint32_t            : 2;
      __IOM uint32_t LPEOC      : 1;            /*!< [4..4] End Of LP Conversion Interrupt Enable                              */
      __IOM uint32_t LPCOL      : 1;            /*!< [5..5] LP Trigger Collision Interrupt Enable                              */
            uint32_t            : 26;
    } IEN_b;
  } ;
  
  union {
    __IOM uint32_t IPND;                        /*!< (@ 0x00000034) ADC Interrupt Pending Register                             */
    
    struct {
      __IOM uint32_t HPEOC      : 1;            /*!< [0..0] End Of HP Conversion Interrupt Pending                             */
      __IOM uint32_t HPCOL      : 1;            /*!< [1..1] HP Trigger Collision Interrupt Pending                             */
            uint32_t            : 2;
      __IOM uint32_t LPEOC      : 1;            /*!< [4..4] End Of LP Conversion Interrupt Pending                             */
      __IOM uint32_t LPCOL      : 1;            /*!< [5..5] LP Trigger Collision Interrupt Pending                             */
            uint32_t            : 26;
    } IPND_b;
  } ;
  
  union {
    __IOM uint32_t EIPND;                       /*!< (@ 0x00000038) ADC Enabled Interrupt Pending Register                     */
    
    struct {
      __IOM uint32_t HPEOC      : 1;            /*!< [0..0] Enabled End Of HP Conversion Interrupt Pending                     */
      __IOM uint32_t HPCOL      : 1;            /*!< [1..1] Enabled HP Trigger Collision Interrupt Pending                     */
            uint32_t            : 2;
      __IOM uint32_t LPEOC      : 1;            /*!< [4..4] Enabled End Of LP Conversion Interrupt Pending                     */
      __IOM uint32_t LPCOL      : 1;            /*!< [5..5] Enabled LP Trigger Collision Interrupt Pending                     */
            uint32_t            : 26;
    } EIPND_b;
  } ;
} ADC_Type;                                     /*!< Size = 60 (0x3c)                                                          */



/* =========================================================================================================================== */
/* ================                                           DWDG                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Digital Watchdog (DWDG)
  */

typedef struct {                                /*!< (@ 0x40007000) DWDG Structure                                             */
  
  union {
    __IOM uint32_t CKSEL;                       /*!< (@ 0x00000000) DWDG Clock Select Register                                 */
    
    struct {
      __IOM uint32_t CKSEL      : 3;            /*!< [2..0] DWDG Clock Selection                                               */
            uint32_t            : 29;
    } CKSEL_b;
  } ;
  
  union {
    __IOM uint32_t RR;                          /*!< (@ 0x00000004) DWDG Reload Register                                       */
    
    struct {
      __IOM uint32_t RR         : 16;           /*!< [15..0] Reload Value                                                      */
            uint32_t            : 16;
    } RR_b;
  } ;
  
  union {
    __IOM uint32_t TRG;                         /*!< (@ 0x00000008) DWDG Trigger Register                                      */
    
    struct {
      __IOM uint32_t TRG        : 8;            /*!< [7..0] Trigger Value                                                      */
            uint32_t            : 24;
    } TRG_b;
  } ;
  
  union {
    __IM  uint32_t CNT;                         /*!< (@ 0x0000000C) DWDG Counter Register                                      */
    
    struct {
      __IM  uint32_t CNT        : 16;           /*!< [15..0] Counter Value                                                     */
            uint32_t            : 16;
    } CNT_b;
  } ;
} DWDG_Type;                                    /*!< Size = 16 (0x10)                                                          */



/* =========================================================================================================================== */
/* ================                                           WWDG                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Window Watchdog and Wakeup Timer (WWDG)
  */

typedef struct {                                /*!< (@ 0x40008000) WWDG Structure                                             */
  __IOM uint32_t  STOP;                         /*!< (@ 0x00000000) WWDG Counter Stop Register                                 */
  
  union {
    __IOM uint32_t CKSEL;                       /*!< (@ 0x00000004) WWDG Clock Select Register                                 */
    
    struct {
      __IOM uint32_t CKSEL      : 3;            /*!< [2..0] WWDG Clock Selection                                               */
            uint32_t            : 29;
    } CKSEL_b;
  } ;
  
  union {
    __IOM uint32_t TWIN;                        /*!< (@ 0x00000008) WWDG Trigger Window Register                               */
    
    struct {
      __IOM uint32_t TWIN       : 8;            /*!< [7..0] Trigger Window                                                     */
            uint32_t            : 24;
    } TWIN_b;
  } ;
  
  union {
    __IOM uint32_t TRG;                         /*!< (@ 0x0000000C) WWDG Trigger Register                                      */
    
    struct {
      __IOM uint32_t TRG        : 8;            /*!< [7..0] Trigger Value                                                      */
            uint32_t            : 24;
    } TRG_b;
  } ;
  
  union {
    __IM  uint32_t CNT;                         /*!< (@ 0x00000010) WWDG Counter Register                                      */
    
    struct {
      __IM  uint32_t CNT        : 8;            /*!< [7..0] Counter Value                                                      */
            uint32_t            : 24;
    } CNT_b;
  } ;
} WWDG_Type;                                    /*!< Size = 20 (0x14)                                                          */



/* =========================================================================================================================== */
/* ================                                           BEMFC                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Back-EMF Comparator (BEMFC)
  */

typedef struct {                                /*!< (@ 0x40009000) BEMFC Structure                                            */
  
  union {
    __IOM uint32_t CR0;                         /*!< (@ 0x00000000) BEMFC Control Register 0                                   */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] BEMFC Enable                                                       */
            uint32_t            : 3;
      __IOM uint32_t BLKT0      : 4;            /*!< [7..4] Phase 0 Blank Time                                                 */
      __IOM uint32_t BLKT1      : 4;            /*!< [11..8] Phase 1 Blank Time                                                */
            uint32_t            : 4;
      __IOM uint32_t INV0       : 1;            /*!< [16..16] Phase 0 Input Inverter                                           */
      __IOM uint32_t INV1       : 1;            /*!< [17..17] Phase 1 Input Inverter                                           */
            uint32_t            : 2;
      __IOM uint32_t DGL0       : 2;            /*!< [21..20] Phase 0 Deglitch Filter                                          */
            uint32_t            : 2;
      __IOM uint32_t DGL1       : 2;            /*!< [25..24] Phase 1 Deglitch Filter                                          */
            uint32_t            : 6;
    } CR0_b;
  } ;
  
  union {
    __IOM uint32_t CR1;                         /*!< (@ 0x00000004) BEMFC Control Register 1                                   */
    
    struct {
      __IOM uint32_t ITS0       : 2;            /*!< [1..0] Phase 0 Interrupt Trigger Source                                   */
      __IOM uint32_t DTP0       : 2;            /*!< [3..2] Phase 0 Detection Trigger Period                                   */
      __IOM uint32_t DTS0       : 4;            /*!< [7..4] Phase 0 Detection Trigger Source                                   */
      __IOM uint32_t ITS1       : 2;            /*!< [9..8] Phase 1 Interrupt Trigger Source                                   */
      __IOM uint32_t DTP1       : 2;            /*!< [11..10] Phase 1 Detection Trigger Period                                 */
      __IOM uint32_t DTS1       : 4;            /*!< [15..12] Phase 1 Detection Trigger Source                                 */
            uint32_t            : 16;
    } CR1_b;
  } ;
  
  union {
    __IM  uint32_t SR;                          /*!< (@ 0x00000008) BEMFC Status Register                                      */
    
    struct {
      __IM  uint32_t CD0        : 1;            /*!< [0..0] Phase 0 Crossing Detection Output                                  */
      __IM  uint32_t CD1        : 1;            /*!< [1..1] Phase 1 Crossing Detection Output                                  */
            uint32_t            : 30;
    } SR_b;
  } ;
  
  union {
    __IOM uint32_t IEN;                         /*!< (@ 0x0000000C) BEMFC Interrupt Enable Register                            */
    
    struct {
      __IOM uint32_t PI0        : 1;            /*!< [0..0] Phase 0 Interrupt Enable                                           */
      __IOM uint32_t PI1        : 1;            /*!< [1..1] Phase 1 Interrupt Enable                                           */
            uint32_t            : 30;
    } IEN_b;
  } ;
  
  union {
    __IOM uint32_t IPND;                        /*!< (@ 0x00000010) BEMFC Interrupt Pending Register                           */
    
    struct {
      __IOM uint32_t PI0        : 1;            /*!< [0..0] Phase 0 Interrupt Pending                                          */
      __IOM uint32_t PI1        : 1;            /*!< [1..1] Phase 1 Interrupt Pending                                          */
            uint32_t            : 30;
    } IPND_b;
  } ;
  
  union {
    __IOM uint32_t EIPND;                       /*!< (@ 0x00000014) BEMFC Enabled Interrupt Pending Register                   */
    
    struct {
      __IOM uint32_t PI0        : 1;            /*!< [0..0] Enabled Phase 0 Interrupt Pending                                  */
      __IOM uint32_t PI1        : 1;            /*!< [1..1] Enabled Phase 1 Interrupt Pending                                  */
            uint32_t            : 30;
    } EIPND_b;
  } ;
} BEMFC_Type;                                   /*!< Size = 24 (0x18)                                                          */



/* =========================================================================================================================== */
/* ================                                            SPI                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Serial Peripheral Interface (SPI)
  */

typedef struct {                                /*!< (@ 0x4000A000) SPI Structure                                              */
  
  union {
    __IOM uint32_t CR;                          /*!< (@ 0x00000000) SPI Control Register                                       */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] SPI Enable                                                         */
      __IOM uint32_t CPHA       : 1;            /*!< [1..1] Clock Phase                                                        */
      __IOM uint32_t CPOL       : 1;            /*!< [2..2] Clock Polarity                                                     */
      __IOM uint32_t LSBF       : 1;            /*!< [3..3] LSB First                                                          */
      __IOM uint32_t DWID       : 2;            /*!< [5..4] Data Word Width                                                    */
      __IOM uint32_t CSINV      : 1;            /*!< [6..6] Chip Select Inversion                                              */
      __IOM uint32_t CSACT      : 1;            /*!< [7..7] Chip Select Active Period                                          */
      __IOM uint32_t SPIC       : 3;            /*!< [10..8] SPI Clock Speed                                                   */
            uint32_t            : 1;
      __IOM uint32_t TXFCV      : 4;            /*!< [15..12] TX FIFO Compare Value                                            */
      __IOM uint32_t RXFCV      : 4;            /*!< [19..16] RX FIFO Compare Value                                            */
            uint32_t            : 12;
    } CR_b;
  } ;
  
  union {
    __IOM uint32_t SR;                          /*!< (@ 0x00000004) SPI Status Register                                        */
    
    struct {
      __IM  uint32_t BUSY       : 1;            /*!< [0..0] SPI Busy                                                           */
            uint32_t            : 3;
      __IM  uint32_t TXFE       : 1;            /*!< [4..4] TX FIFO Empty                                                      */
      __IM  uint32_t TXFF       : 1;            /*!< [5..5] TX FIFO Full                                                       */
      __IM  uint32_t TXFC       : 1;            /*!< [6..6] TX FIFO Compare                                                    */
      __IOM uint32_t TXFO       : 1;            /*!< [7..7] TX FIFO Overflow                                                   */
      __IOM uint32_t TXFFILL    : 4;            /*!< [11..8] TX FIFO Fill Level                                                */
      __IM  uint32_t RXFE       : 1;            /*!< [12..12] RX FIFO Empty                                                    */
      __IM  uint32_t RXFF       : 1;            /*!< [13..13] RX FIFO Full                                                     */
      __IM  uint32_t RXFC       : 1;            /*!< [14..14] RX FIFO Compare                                                  */
      __IOM uint32_t RXFO       : 1;            /*!< [15..15] RX FIFO Overflow                                                 */
      __IOM uint32_t RXFFILL    : 4;            /*!< [19..16] RX FIFO Fill Level                                               */
            uint32_t            : 12;
    } SR_b;
  } ;
  
  union {
    __IOM uint32_t TXF;                         /*!< (@ 0x00000008) SPI Transmit FIFO                                          */
    
    struct {
      __IOM uint32_t DATA       : 32;           /*!< [31..0] TX Data                                                           */
    } TXF_b;
  } ;
  
  union {
    __IM  uint32_t RXF;                         /*!< (@ 0x0000000C) SPI Receive FIFO                                           */
    
    struct {
      __IM  uint32_t DATA       : 32;           /*!< [31..0] RX Data                                                           */
    } RXF_b;
  } ;
  
  union {
    __IOM uint32_t IEN;                         /*!< (@ 0x00000010) SPI Interrupt Enable Register                              */
    
    struct {
      __IOM uint32_t TXFE       : 1;            /*!< [0..0] TX FIFO Empty Interrupt Enable                                     */
      __IOM uint32_t TXFNF      : 1;            /*!< [1..1] TX FIFO Not Full Interrupt Enable                                  */
      __IOM uint32_t TXFC       : 1;            /*!< [2..2] TX FIFO Compare Interrupt Enable                                   */
      __IOM uint32_t TXFO       : 1;            /*!< [3..3] TX FIFO Overflow Interrupt Enable                                  */
      __IOM uint32_t RXFNE      : 1;            /*!< [4..4] RX FIFO Not Empty Interrupt Enable                                 */
      __IOM uint32_t RXFF       : 1;            /*!< [5..5] RX FIFO Full Interrupt Enable                                      */
      __IOM uint32_t RXFC       : 1;            /*!< [6..6] RX FIFO Compare Interrupt Enable                                   */
      __IOM uint32_t RXFO       : 1;            /*!< [7..7] RX FIFO Overflow Interrupt Enable                                  */
            uint32_t            : 24;
    } IEN_b;
  } ;
  
  union {
    __IOM uint32_t IPND;                        /*!< (@ 0x00000014) SPI Interrupt Pending Register                             */
    
    struct {
      __IOM uint32_t TXFE       : 1;            /*!< [0..0] TX FIFO Empty Interrupt Pending                                    */
      __IOM uint32_t TXFNF      : 1;            /*!< [1..1] TX FIFO Not Full Interrupt Pending                                 */
      __IOM uint32_t TXFC       : 1;            /*!< [2..2] TX FIFO Compare Interrupt Pending                                  */
      __IOM uint32_t TXFO       : 1;            /*!< [3..3] TX FIFO Overflow Interrupt Pending                                 */
      __IOM uint32_t RXFNE      : 1;            /*!< [4..4] RX FIFO Not Empty Interrupt Pending                                */
      __IOM uint32_t RXFF       : 1;            /*!< [5..5] RX FIFO Full Interrupt Pending                                     */
      __IOM uint32_t RXFC       : 1;            /*!< [6..6] RX FIFO Compare Interrupt Pending                                  */
      __IOM uint32_t RXFO       : 1;            /*!< [7..7] RX FIFO Overflow Interrupt Pending                                 */
            uint32_t            : 24;
    } IPND_b;
  } ;
  
  union {
    __IOM uint32_t EIPND;                       /*!< (@ 0x00000018) SPI Enabled Interrupt Pending Register                     */
    
    struct {
      __IOM uint32_t TXFE       : 1;            /*!< [0..0] Enabled TX FIFO Empty Interrupt Pending                            */
      __IOM uint32_t TXFNF      : 1;            /*!< [1..1] Enabled TX FIFO Not Full Interrupt Pending                         */
      __IOM uint32_t TXFC       : 1;            /*!< [2..2] Enabled TX FIFO Compare Interrupt Pending                          */
      __IOM uint32_t TXFO       : 1;            /*!< [3..3] Enabled TX FIFO Overflow Interrupt Pending                         */
      __IOM uint32_t RXFNE      : 1;            /*!< [4..4] Enabled RX FIFO Not Empty Interrupt Pending                        */
      __IOM uint32_t RXFF       : 1;            /*!< [5..5] Enabled RX FIFO Full Interrupt Pending                             */
      __IOM uint32_t RXFC       : 1;            /*!< [6..6] Enabled RX FIFO Compare Interrupt Pending                          */
      __IOM uint32_t RXFO       : 1;            /*!< [7..7] Enabled RX FIFO Overflow Interrupt Pending                         */
            uint32_t            : 24;
    } EIPND_b;
  } ;
} SPI_Type;                                     /*!< Size = 28 (0x1c)                                                          */



/* =========================================================================================================================== */
/* ================                                            LIN                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief LIN Interface (LIN)
  */

typedef struct {                                /*!< (@ 0x4000B000) LIN Structure                                              */
  
  union {
    __IOM uint32_t CR;                          /*!< (@ 0x00000000) LIN Control Register                                       */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] LIN Enable                                                         */
      __IOM uint32_t RXFT       : 3;            /*!< [3..1] RX Filter Time                                                     */
      __IOM uint32_t OCFT       : 2;            /*!< [5..4] Overcurrent Filter Time                                            */
      __IOM uint32_t LAIS       : 1;            /*!< [6..6] LINUART Alternative Input Select                                   */
            uint32_t            : 1;
      __IOM uint32_t TXOS       : 2;            /*!< [9..8] TX Output Select                                                   */
      __IOM uint32_t SR         : 2;            /*!< [11..10] LIN Slew Rate Select                                             */
      __IOM uint32_t DOMTOEN    : 1;            /*!< [12..12] Dominant Timeout Detection Enable                                */
      __IOM uint32_t LOM        : 1;            /*!< [13..13] LIN Operating Mode                                               */
            uint32_t            : 2;
      __IOM uint32_t TAIS0      : 1;            /*!< [16..16] TIM0 Alternative Input Select                                    */
      __IOM uint32_t TAIS1      : 1;            /*!< [17..17] TIM1 Alternative Input Select                                    */
            uint32_t            : 14;
    } CR_b;
  } ;
  
  union {
    __IOM uint32_t DO;                          /*!< (@ 0x00000004) LIN Data Out Register                                      */
    
    struct {
      __IOM uint32_t DO         : 1;            /*!< [0..0] LIN Data Out                                                       */
            uint32_t            : 31;
    } DO_b;
  } ;
  
  union {
    __IM  uint32_t DI;                          /*!< (@ 0x00000008) LIN Data In Register                                       */
    
    struct {
      __IM  uint32_t DI         : 1;            /*!< [0..0] LIN Data In                                                        */
            uint32_t            : 31;
    } DI_b;
  } ;
  
  union {
    __IOM uint32_t BSMCR;                       /*!< (@ 0x0000000C) LIN Bus Shunt Control Register                             */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] Auto-Addressing Enable                                             */
      __IOM uint32_t SWPU       : 1;            /*!< [1..1] Switch Pull-Up Resistor                                            */
      __IOM uint32_t SWCS       : 1;            /*!< [2..2] Switch Current Source                                              */
            uint32_t            : 1;
      __IOM uint32_t BSMS       : 1;            /*!< [4..4] BSM Sampling Enable                                                */
      __IOM uint32_t BSMG       : 2;            /*!< [6..5] BSM Pre-Amplifier Gain                                             */
            uint32_t            : 25;
    } BSMCR_b;
  } ;
  
  union {
    __IOM uint32_t IEN;                         /*!< (@ 0x00000010) LIN Interrupt Enable Register                              */
    
    struct {
      __IOM uint32_t LINFE      : 1;            /*!< [0..0] LIN Input Falling Edge Interrupt Enable                            */
      __IOM uint32_t LINRE      : 1;            /*!< [1..1] LIN Input Rising Edge Interrupt Enable                             */
      __IOM uint32_t OC         : 1;            /*!< [2..2] Overcurrent Interrupt Enable                                       */
      __IOM uint32_t DOMTO      : 1;            /*!< [3..3] Dominant Timeout Interrupt Enable                                  */
      __IOM uint32_t BEND       : 1;            /*!< [4..4] Bit-End Interrupt Enable                                           */
            uint32_t            : 27;
    } IEN_b;
  } ;
  
  union {
    __IOM uint32_t IPND;                        /*!< (@ 0x00000014) LIN Interrupt Pending Register                             */
    
    struct {
      __IOM uint32_t LINFE      : 1;            /*!< [0..0] LIN Input Falling Edge Interrupt Pending                           */
      __IOM uint32_t LINRE      : 1;            /*!< [1..1] LIN Input Rising Edge Interrupt Pending                            */
      __IOM uint32_t OC         : 1;            /*!< [2..2] Overcurrent Interrupt Pending                                      */
      __IOM uint32_t DOMTO      : 1;            /*!< [3..3] Dominant Timeout Interrupt Pending                                 */
      __IOM uint32_t BEND       : 1;            /*!< [4..4] Bit-End Interrupt Pending                                          */
            uint32_t            : 27;
    } IPND_b;
  } ;
  
  union {
    __IOM uint32_t EIPND;                       /*!< (@ 0x00000018) LIN Enabled Interrupt Pending Register                     */
    
    struct {
      __IOM uint32_t LINFE      : 1;            /*!< [0..0] LIN Enabled Input Falling Edge Interrupt Pending                   */
      __IOM uint32_t LINRE      : 1;            /*!< [1..1] LIN Enabled Input Rising Edge Interrupt Pending                    */
      __IOM uint32_t OC         : 1;            /*!< [2..2] Enabled Overcurrent Interrupt Pending                              */
      __IOM uint32_t DOMTO      : 1;            /*!< [3..3] Enabled Dominant Timeout Interrupt Pending                         */
      __IOM uint32_t BEND       : 1;            /*!< [4..4] Enabled Bit-End Interrupt Pending                                  */
            uint32_t            : 27;
    } EIPND_b;
  } ;
} LIN_Type;                                     /*!< Size = 28 (0x1c)                                                          */



/* =========================================================================================================================== */
/* ================                                           FLASH                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Flash Memory (FLASH)
  */

typedef struct {                                /*!< (@ 0x00200000) FLASH Structure                                            */
  __IOM FLASH_MAIN_Type MAIN[128];              /*!< (@ 0x00000000) MAIN Array                                                 */
  __IM  uint32_t  RESERVED[122880];
  
  union {
    __IOM uint32_t CR;                          /*!< (@ 0x00080000) Flash Control Register                                     */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] Flash Enable                                                       */
            uint32_t            : 3;
      __IOM uint32_t CHIP       : 1;            /*!< [4..4] Chip Erase Enable                                                  */
      __IOM uint32_t ERA_STRT   : 1;            /*!< [5..5] Start Erase Operation                                              */
            uint32_t            : 1;
      __IOM uint32_t PRG_STRT   : 1;            /*!< [7..7] Start Program Operation                                            */
            uint32_t            : 24;
    } CR_b;
  } ;
  
  union {
    __IOM uint32_t SR;                          /*!< (@ 0x00080004) Flash Status Register                                      */
    
    struct {
      __IM  uint32_t RDY        : 1;            /*!< [0..0] Ready                                                              */
            uint32_t            : 1;
      __IOM uint32_t SBC        : 1;            /*!< [2..2] Single Bit Error                                                   */
      __IOM uint32_t DED        : 1;            /*!< [3..3] Double Bit Error                                                   */
      __IOM uint32_t BLNK       : 1;            /*!< [4..4] Blank Check (Any Array)                                            */
      __IOM uint32_t BLNKE      : 1;            /*!< [5..5] Blank Check (EEPROM)                                               */
      __IOM uint32_t ABLNK      : 1;            /*!< [6..6] Accumulated Blank Check (Any Array)                                */
      __IOM uint32_t ABLNKE     : 1;            /*!< [7..7] Accumulated Blank Check (EEPROM)                                   */
      __IOM uint32_t SBCM       : 1;            /*!< [8..8] Single Bit Error (MAIN array)                                      */
      __IOM uint32_t DEDM       : 1;            /*!< [9..9] Double Bit Error (MAIN array)                                      */
      __IOM uint32_t SBCE       : 1;            /*!< [10..10] Single Bit Error (EEPROM array)                                  */
      __IOM uint32_t DEDE       : 1;            /*!< [11..11] Double Bit Error (EEPROM array)                                  */
      __IOM uint32_t SBCN       : 1;            /*!< [12..12] Single Bit Error (NVR array)                                     */
      __IOM uint32_t DEDN       : 1;            /*!< [13..13] Double Bit Error (NVR array)                                     */
            uint32_t            : 18;
    } SR_b;
  } ;
  __IOM uint32_t  MULA;                         /*!< (@ 0x00080008) MAIN Array Unlock Register A                               */
  __IOM uint32_t  MULB;                         /*!< (@ 0x0008000C) MAIN Array Unlock Register B                               */
  __IOM uint32_t  EULA;                         /*!< (@ 0x00080010) EEPROM Unlock Register A                                   */
  __IOM uint32_t  EULB;                         /*!< (@ 0x00080014) EEPROM Unlock Register B                                   */
  __IOM uint32_t  NULA;                         /*!< (@ 0x00080018) NVR Unlock Register A                                      */
  __IOM uint32_t  NULB;                         /*!< (@ 0x0008001C) NVR Unlock Register B                                      */
  
  union {
    __IOM uint32_t IEN;                         /*!< (@ 0x00080020) Flash Interrupt Enable Register                            */
    
    struct {
      __IOM uint32_t SBC        : 1;            /*!< [0..0] Single Bit Error Correction Interrupt Enable                       */
      __IOM uint32_t DED        : 1;            /*!< [1..1] Double Bit Error Detection Interrupt Enable                        */
            uint32_t            : 30;
    } IEN_b;
  } ;
  
  union {
    __IOM uint32_t IPND;                        /*!< (@ 0x00080024) Flash Interrupt Pending Register                           */
    
    struct {
      __IOM uint32_t SBC        : 1;            /*!< [0..0] Single Bit Error Correction Interrupt Pending                      */
      __IOM uint32_t DED        : 1;            /*!< [1..1] Double Bit Error Detection Interrupt Pending                       */
            uint32_t            : 30;
    } IPND_b;
  } ;
  
  union {
    __IOM uint32_t EIPND;                       /*!< (@ 0x00080028) Flash Enabled Interrupt Pending Register                   */
    
    struct {
      __IOM uint32_t SBC        : 1;            /*!< [0..0] Enabled Single Bit Error Correction Interrupt Pending              */
      __IOM uint32_t DED        : 1;            /*!< [1..1] Enabled Double Bit Error Detection Interrupt Pending               */
            uint32_t            : 30;
    } EIPND_b;
  } ;
  __IM  uint32_t  RESERVED1[16373];
  __IOM uint32_t  NVR0[64];                     /*!< (@ 0x00090000) NVR Data Sector 0                                          */
  __IM  uint32_t  RESERVED2[16320];
  __IOM uint32_t  EEPROM0[64];                  /*!< (@ 0x000A0000) EEPROM Data Sector 0                                       */
  __IOM uint32_t  EEPROM1[64];                  /*!< (@ 0x000A0100) EEPROM Data Sector 1                                       */
} FLASH_Type;                                   /*!< Size = 655872 (0xa0200)                                                   */



/* =========================================================================================================================== */
/* ================                                            PI                                             ================ */
/* =========================================================================================================================== */


/**
  * @brief Product Identification (PI)
  */

typedef struct {                                /*!< (@ 0x002FFFEC) PI Structure                                               */
  __IM  uint32_t  RESERVED[4];
  
  union {
    __IM  uint32_t VERS;                        /*!< (@ 0x00000010) Device Version                                             */
    
    struct {
      __IM  uint32_t VERS       : 32;           /*!< [31..0] Device Version                                                    */
    } VERS_b;
  } ;
} PI_Type;                                      /*!< Size = 20 (0x14)                                                          */


/** @} */ /* End of group Device_Peripheral_peripherals */


/* =========================================================================================================================== */
/* ================                          Device Specific Peripheral Address Map                           ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_peripheralAddr
  * @{
  */

#define SYSCTRL_BASE                0x40000000UL
#define LGPIO_BASE                  0x40001000UL
#define TIM0_BASE                   0x40002000UL
#define TIM1_BASE                   0x40002100UL
#define LINUART_BASE                0x40003000UL
#define EPWM_BASE                   0x40004000UL
#define CAPCOM_BASE                 0x40005000UL
#define ADC_BASE                    0x40006000UL
#define DWDG_BASE                   0x40007000UL
#define WWDG_BASE                   0x40008000UL
#define BEMFC_BASE                  0x40009000UL
#define SPI_BASE                    0x4000A000UL
#define LIN_BASE                    0x4000B000UL
#define FLASH_BASE                  0x00200000UL
#define PI_BASE                     0x002FFFECUL

/** @} */ /* End of group Device_Peripheral_peripheralAddr */


/* =========================================================================================================================== */
/* ================                                  Peripheral declaration                                   ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_declaration
  * @{
  */

#define SYSCTRL                     ((SYSCTRL_Type*)           SYSCTRL_BASE)
#define LGPIO                       ((LGPIO_Type*)             LGPIO_BASE)
#define TIM0                        ((TIM_Type*)               TIM0_BASE)
#define TIM1                        ((TIM_Type*)               TIM1_BASE)
#define LINUART                     ((LINUART_Type*)           LINUART_BASE)
#define EPWM                        ((EPWM_Type*)              EPWM_BASE)
#define CAPCOM                      ((CAPCOM_Type*)            CAPCOM_BASE)
#define ADC                         ((ADC_Type*)               ADC_BASE)
#define DWDG                        ((DWDG_Type*)              DWDG_BASE)
#define WWDG                        ((WWDG_Type*)              WWDG_BASE)
#define BEMFC                       ((BEMFC_Type*)             BEMFC_BASE)
#define SPI                         ((SPI_Type*)               SPI_BASE)
#define LIN                         ((LIN_Type*)               LIN_BASE)
#define FLASH                       ((FLASH_Type*)             FLASH_BASE)
#define PI                          ((PI_Type*)                PI_BASE)

/** @} */ /* End of group Device_Peripheral_declaration */


/* =========================================  End of section using anonymous unions  ========================================= */
#if defined (__CC_ARM)
  #pragma pop
#elif defined (__ICCARM__)
  /* leave anonymous unions enabled */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic pop
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning restore
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#endif


#ifdef __cplusplus
}
#endif

#endif /* HVC5221D_B1_H */


/** @} */ /* End of group HVC5221D_B1 */

/** @} */ /* End of group TDK-Micronas */
